A New Parallel CODEC Technique for CDMA NoCs

Wang, Jian; Guo, Shize; Chen, Zhe; Li, Yubai; Lu, Zhonghai

doi:10.1109/tie.2017.2786230

Cited by 7 publications

(4 citation statements)

References 25 publications

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“…In Table 4, the ACDMA NoC router implementation results including the area and maximum clock cycle are compared to the CDMA NoCs presented in [1], [11], [13]. The comparison is limited to full NoC routers implemented in the ASIC technology.…”

Section: Acdma-based Nocmentioning

confidence: 99%

Aggregated CDMA Crossbar With Hybrid ARQ for NoCs

Farag

Ahmed

2022

IEEE Access

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Network-on-Chips (NoCs) are the dominant interconnection technique in modern Systemon-Chips (SoCs). NoC routers constitute the physical layer of on-chip interconnects while the medium access technique utilized in NoC routers profoundly impacts the performance and footprint of the router. Code Division Multiple Access (CDMA) is one of the prominent access techniques employed in the physical layer crossbar of NoC routers. Adopted from the wireless communications realm, the CDMA-based crossbar relies on spreading the transmitted data bit on the physical channel using orthogonal codes, summing the data spread from various transmitters, then decoding the received sum using correlation decoders to extract the sent binary bit. However, due to multiple access interference and random channel effects notorious in wireless communications and following the same exact approach in on-chip CDMA interconnects, existing CDMA crossbars are bit-wise architectures where binary data bits are spread and serially communicated on an exclusive digital channel while replicating this configuration to communicate multi-bit packets which increases the crossbar area overhead. We advance an elegant modification to improve the area and power consumption of the classical CDMA crossbars. Aggregated CDMA (ACDMA) relies on high wiring density in modern SoCs in addition to its static nature and relative noise immunity to improve the classical CDMA crossbar architecture by aggregating the transmission of multiple data bits on the same channel which reduces the overhead of ordinary CDMA-based NoCs. In this work, the ACDMA mathematical foundations, crossbar hardware architecture, and full NoC realizations are presented. The implementation results on the 65 nm standardcell ASIC technology show a significant improvement in the resource utilization and power consumption of the ACDMA crossbar and ACDMA-based NoCs compared to the ordinary CDMA and CONNECT NoC counterparts. Moreover, the ACDMA interconnect reliability in AWGN channels is studied and improved using a hybrid ARQ approach tailored to the ACDMA crossbar.

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Section: Acdma-based Nocmentioning

confidence: 99%

Aggregated CDMA Crossbar With Hybrid ARQ for NoCs

Farag

Ahmed

2022

IEEE Access

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“…An input signal controls whether the injector is turned on or not. Three kinds of traffic patterns, namely, uniform, hotspot and bit-reverse, can be applied on the experimental NoCs [2], and NoCs here work in the uniform traffic pattern. According to the pattern, the peripheral injector will generate 10,000,000 packets, 32 40-bit flits in each packet, and inject them to the NoC with a Poisson distribution.…”

Section: ) Functional Testingmentioning

confidence: 99%

“…With the development of nano-technology, more and more cores can be integrated into a single chip [1], e.g., CMP (Chip Multi-Processor) and MPSoC (Multi-Processor System-on-Chip), to satisfy the increasing requirement for computational ability from various electronic systems, such as data center, workstation and measuring instrument, etc. NoC (Networkon-Chip) [2], which is proposed to address the scalability, throughput and reliability issues of on-chip communication, has become the preferred communication infrastructure for many/multi-core platforms, as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

A Benchmark Suite of Hardware Trojans for On-Chip Networks

et al. 2019

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As recently studied, network-on-chip (NoC) suffers growing threats from hardware trojans (HTs), leading to performance degradation or information leakage when it provides communication service in many/multi-core systems. Therefore, defense techniques against NoC HTs experience rapid development in recent years. However, to the best of our knowledge, there are few standard benchmarks developed for the defense techniques evaluation. To address this issue, in this paper, we design a suite of benchmarks which involves multiple NoCs with different HTs, so that researchers can compare various HT defense methods fairly by making use of them. We first briefly introduce the features of target NoC and its infected modules in our benchmarks, and then, detail the design of our NoC HTs in a one-by-one manner. Finally, we evaluate our benchmarks through extensive simulations and report the circuit cost of NoC HTs in terms of area and power consumption, as well as their effects on NoC performance. Besides, comprehensive experiments, including functional testing and side channel analysis are performed to assess the stealthiness of our HTs.INDEX TERMS Benchmarks, hardware trojan, network-on-chip.

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“…In comparison with conventional on-chip communication schemes, the CDMA bus is more suitable for supporting multiple-access communications and it is capable of achieving higher throughput under heavy traffic load conditions. In addition to its use as a multiprocessor bus, the CDMA technique is used as an alternative to a crossbar switch in NoC routers, and a flexible peripheral switch that simplifies interconnection between the CPU core and numerous input/output ports [1,5,12,13].…”

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confidence: 99%

Distributed arbitration scheme for on‐chip CDMA bus with dynamic codeword assignment

2020

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Computation and communication are the two most critical aspects affecting the overall system performance of complex integrated circuits. Technology scaling has enabled the integration of a large number of processing elements (PEs), in the form of intellectual property cores, within complex systems-on-chip (SoCs), thus increasing the computation performance of integrated circuits considerably. However, dealing with data communication among the ever-increasing number of PEs in an SoC environment requires faster and more efficient on-chip interconnection architectures [1][2][3][4]. Most interconnect networks in embedded SoCs rely on a traditional shared bus employing time-division multiplexing (TDM) communication protocols to reuse expensive on-chip interconnect resources. A TDM bus is usually accompanied by scheduling and arbitration overheads, which increases the transmission latency [5]. Furthermore, the lack of parallel transmissions makes the scaling of a TDM-bus-based onchip interconnect difficult, because each added PE decreases the bandwidth available to the other PEs. Network-on-chip (NoC) has been proposed to address the scalability, latency, throughput, and reliability issues of TDM on-chip communication [6]. The PEs in an NoC system communicate data packets through routers and communication links arranged in a specific network topology. The locality of interconnections provides a high level of parallelism, because all the links and routers in the NoC can operate simultaneously on different

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A New Parallel CODEC Technique for CDMA NoCs

Cited by 7 publications

References 25 publications

Aggregated CDMA Crossbar With Hybrid ARQ for NoCs

Aggregated CDMA Crossbar With Hybrid ARQ for NoCs

A Benchmark Suite of Hardware Trojans for On-Chip Networks

Distributed arbitration scheme for on‐chip CDMA bus with dynamic codeword assignment

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