Distributed arbitration scheme for on‐chip CDMA bus with dynamic codeword assignment

Abstract

Computation and communication are the two most critical aspects affecting the overall system performance of complex integrated circuits. Technology scaling has enabled the integration of a large number of processing elements (PEs), in the form of intellectual property cores, within complex systems-on-chip (SoCs), thus increasing the computation performance of integrated circuits considerably. However, dealing with data communication among the ever-increasing number of PEs in an SoC environment requires faster and more efficient on-chip interconnection architectures [1][2][3][4]. Most interconnect networks in embedded SoCs rely on a traditional shared bus employing time-division multiplexing (TDM) communication protocols to reuse expensive on-chip interconnect resources. A TDM bus is usually accompanied by scheduling and arbitration overheads, which increases the transmission latency [5]. Furthermore, the lack of parallel transmissions makes the scaling of a TDM-bus-based onchip interconnect difficult, because each added PE decreases the bandwidth available to the other PEs. Network-on-chip (NoC) has been proposed to address the scalability, latency, throughput, and reliability issues of TDM on-chip communication [6]. The PEs in an NoC system communicate data packets through routers and communication links arranged in a specific network topology. The locality of interconnections provides a high level of parallelism, because all the links and routers in the NoC can operate simultaneously on different