A Benchmark Suite of Hardware Trojans for On-Chip Networks

Wang, Jian; Guo, Shize; Chen, Zhe; Zhang, Tao

doi:10.1109/access.2019.2929274

Cited by 8 publications

(5 citation statements)

References 30 publications

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“…These extensions may include leveraging FIB to create opens and shorts within circuits, particularly with regard to security-critical nets involved in on-chip tamper detection and response mechanisms. Also, we will target more emerging device models such as large on-chip communication infrastructure [34] and 3D ICs [35].…”

Section: Discussionmentioning

confidence: 99%

Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and Resource

Gao,

Biswas,

Asadi

et al. 2024

Cryptography

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Recent decades have witnessed a remarkable pace of innovation and performance improvements in integrated circuits (ICs), which have become indispensable in an array of critical applications ranging from military infrastructure to personal healthcare. Meanwhile, recent developments have brought physical security to the forefront of concern, particularly considering the valuable assets handled and stored within ICs. Among the various invasive attack vectors, micro-probing attacks have risen as a particularly menacing threat. These attacks leverage advanced focused ion beam (FIB) systems to enable post-silicon secret eavesdropping and circuit modifications with minimal traceability. As an evolved variant of micro-probing attacks, reroute attacks possess the ability to actively disable built-in shielding measures, granting access to the security-sensitive signals concealed beneath. To address and counter these emerging challenges, we introduce a layout-level framework known as Detour-RS. This framework is designed to automatically assess potential vulnerabilities, offering a systematic approach to identifying and mitigating exploitable weaknesses. Specifically, we employed a combination of linear and nonlinear programming-based approaches to identify the layout-aware attack costs in reroute attempts given specific target assets. The experimental results indicate that shielded designs outperform non-shielded structures against reroute attacks. Furthermore, among the two-layer shield configurations, the orthogonal layout exhibits better performance compared to the parallel arrangement. Furthermore, we explore both independent and dependent scenarios, where the latter accounts for potential interference among circuit edit locations. Notably, our results demonstrate a substantial near 50% increase in attack cost when employing the more realistic dependent estimation approach. In addition, we also propose time and gas consumption metrics to evaluate the resource consumption of the attackers, which provides a perspective for evaluating reroute attack efforts. We have collected the results for different categories of target assets and also the average resource consumption for each via, required during FIB reroute attack.

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Section: Discussionmentioning

confidence: 99%

Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and Resource

Gao,

Biswas,

Asadi

et al. 2024

Cryptography

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“…For instance, chiplet design/fabrication or/and interposer fabrication team may have intentions to incorporate hardware Trojans to intercept sensitive communication among chiplets [53], resulting in unauthorized physical disruptions to the global on-chip infrastructure, such as the power distribution network (PDN), leading to the induction of faults in other chiplets [54]. It also could be substantial performance degradation that may result from injecting a large volume of fake traffic into the on-chip communication interface [55]. Note that while the current HI solutions may primarily be implemented internally by prominent semiconductor companies such as AMD and Intel [56], more malicious implants will be witnessed over time due to the ever-increasing emergence of third parties.…”

Section: B Case C2: Malicious Hardware Modificationmentioning

confidence: 99%

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Sami,

Zhang,

Shuvo

et al. 2024

IEEE Access

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The semiconductor industry has adopted heterogeneous integration (HI), incorporating modular intellectual property (IP) blocks (chiplets) into a unified system-in-package (SiP) to overcome the slowdown in Moore's Law and Dennard scaling and to respond to the increasing demand for advanced integrated circuits (ICs). Despite the manifold benefits of HI, such as enhanced performance, reduced area overhead, and improved yield, this transformation has also led to security vulnerabilities in the SiP supply chain and in-field operations, ranging from chiplet piracy and SiP reverse engineering (RE) to information leakage. Although conventional countermeasures provide the desired robustness for monolithic ICs, they are insufficient for addressing these challenges in the context of HI. To address these concerns, this paper presents a novel root-of-trust architecture, augmenting the process of integration using a centralized chiplet hardware security module (CHSM), aiming to provide comprehensive and robust protection throughout the SiP supply chain and in-field operations. Also, the proposed architecture equipped with the CHSM effectively addresses potential security breaches while providing robust protection against zero-day attacks through its reconfigurable capabilities. Throughout five detailed case studies, this paper performs a comprehensive security analysis to illustrate the resilience of CHSM against contemporary attack scenarios in the HI domain.

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“…A trojan is a unique circuit that performs specific malicious activity [21]. Trojan considered in our proposed work will change the functionality of the circuit.…”

Section: A Design Of Trojan Threat Modelmentioning

confidence: 99%

Hardware Trojan Detection based on Testability Measures in Gate Level Netlists using Machine Learning

Thejaswini¹,

H²,

Aravind³

et al. 2022

IJACSA

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Modern integrated circuit design manufacturing involves outsourcing intellectual property to third-party vendors to cut down on overall cost. Since there is a partial surrender of control, these third-party vendors may introduce malicious circuit commonly known as Hardware Trojan into the system in such a way that it goes undetected by the end-users' default security measures. Therefore, to mitigate the threat of functionality change caused by the Trojan, a technique is proposed based on the testability measures in gate level netlists using Machine Learning. The proposed technique detects the presence of Trojan from the gate-level description of nodes using controllability and observability values. Various Machine Learning models are implemented to classify the nodes as Trojan infected and non-infected. The efficiency of linear discriminant analysis obtains an accuracy of 92.85 %, precision of 99.9 %, recall of 80%, and F1 score of 88.8% with a latency of around 0.9 ms.

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A Benchmark Suite of Hardware Trojans for On-Chip Networks

Cited by 8 publications

References 30 publications

Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and Resource

Detour-RS: Reroute Attack Vulnerability Assessment with Awareness of the Layout and Resource

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Hardware Trojan Detection based on Testability Measures in Gate Level Netlists using Machine Learning

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