A new multitime programmable non-volatile memory cell using high voltage NMOS

Xu, Shunqiang; Wang, Hongyi; Wu, Jianfei; Zheng, Liming; Diao, Jietao

doi:10.1016/j.microrel.2018.07.089

Cited by 2 publications

(1 citation statement)

References 10 publications

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“…[1][2][3][4][5][6] The key advantage of logic NVM solutions over traditional eNVM methods is that they are completely compliant with CMOS logic processes, which results in lower costs and improved integration flexibility. [7][8][9][10][11][12][13][14][15] The scaling of CMOS drives the improvement of performance and cost reduction for a number of applications. [16][17][18] However, uncontrollable short channel effects has become one of the main challenges that conventional planar MOSFETs faces beyond technology nodes scales beyond 20 nm.…”

Section: Introductionmentioning

confidence: 99%

Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies

Chuang

Lin

King

2021

Jpn. J. Appl. Phys.

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This paper presents a new multiple-time programmable (MTP) memory cell that features an n-well as the erasing gate and is implemented in a 16 nm FinFET technology process. It is composed of slot contacts placed beside a metal gate for lateral coupling to the floating gate, while an n-well with a floating gate laid on top of it functions as erasing terminal. With adjusted slot contact length, a programming gate (PG) coupling ratio can be designed for the optimized program, erase and read operations to best meet the needs for logic non-volatile memory array development. An increase in the PG coupling ratio provides an increasing read current and lower leakage current, which brings about an improved read window in a larger array. Good endurance test results and disturb immunity were also demonstrated on these new MPT cells.

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Section: Introductionmentioning

confidence: 99%

Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies

Chuang

Lin

King

2021

Jpn. J. Appl. Phys.

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Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

2022

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Increasing the energy efficiency of deep learning systems is critical for improving the cognitive capability of edge devices, often battery operated, as well as for data centers, constrained by the total power envelope. Specialized architectures accelerated by analog vector-matrix multipliers (VMMs) can reduce by orders of magnitude the energy per operation, since the reduced precision of analog computation does not undermine the classification accuracy of the neural network. We show an analog vector-matrix multiplier fabricated with industry-standard 0.18 µm CMOS process, exploiting a single-transistor non-volatile analog memory cell and dedicated technology circuit co-design. The design is focused on implementation in neural networks performing offline training. The VMM performs the analog multiplication of a vector of inputs, encoded in the duration of time pulses, times a matrix of weights, encoded in the programmable currents of the memory cells. A 1.72 µm 2 memory cell is realized with a single transistor with floating gate, which can be operated as a two-terminal analog memristive device with more than 64 programmable current levels and high I high /I low ratio (> 10 3 ), tuned by the charge injected in the floating gate. A small-area charge amplifier is used to convert the multiply and accumulate operation result into a voltage. System-level projections based on our measurements and simulations provide a throughput of 333.17 GOps/s and an energy efficiency of 122.3 TOps/J, higher than comparable-precision VMMs reported in the literature, and an equivalent area per cell down to 2.15 µm 2 , lower than any similar state-ofthe-art solution. Of critical importance in view of translation to industry, our proposal uses in a new way an industry-standard low-cost single-poly CMOS process flow.

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A new multitime programmable non-volatile memory cell using high voltage NMOS

Cited by 2 publications

References 10 publications

Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies

Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

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