Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies

Abstract

This paper presents a new multiple-time programmable (MTP) memory cell that features an n-well as the erasing gate and is implemented in a 16 nm FinFET technology process. It is composed of slot contacts placed beside a metal gate for lateral coupling to the floating gate, while an n-well with a floating gate laid on top of it functions as erasing terminal. With adjusted slot contact length, a programming gate (PG) coupling ratio can be designed for the optimized program, erase and read operations to best meet the needs for logic non-volatile memory array development. An increase in the PG coupling ratio provides an increasing read current and lower leakage current, which brings about an improved read window in a larger array. Good endurance test results and disturb immunity were also demonstrated on these new MPT cells.