A new modulo 2/sup a/+1 multiplier

Wrzyszcz, A.; Milford, D.

doi:10.1109/iccd.1993.393303

Cited by 16 publications

(18 citation statements)

References 7 publications

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“…Three low-cost classes of moduli (in their order of appearance) are an even modulus m i = 2 b , an odd modulus m i = 2 b − 1, and m i = 2 b + 1, for which hardware implementations of the basic arithmetic circuits can be found: two-operand adders [8,[11][12][13]17,35], multi-operand modular adders (MOMAs) and residue generators (used to build forward converters) [21,23], multipliers [16,34,35], multiplier-accumulators (MACs) and complete residue datapaths [9,14,24,25].…”

Section: Introductionmentioning

confidence: 99%

Design of Reverse Converters for a New Flexible RNS Five-Moduli Set $$\{ 2^k, 2^n-1, 2^n+1, 2^{n+1}-1, 2^{n-1}-1 \}$$ { 2 k , 2 n - 1 , 2 n + 1 , 2 n + 1 - 1 , 2 n - 1 - 1 } (n Even)

Patronik

Piestrak

2017

Circuits Syst Signal Process

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This paper presents the design methods of residue-to-binary (reverse) converters for the new flexible balanced five-moduli set {2 k , 2 n − 1, 2 n + 1, 2 n+1 − 1, 2 n−1 − 1} for the pairs of positive integers n ≥ 4 (even) and any k > 0, which can provide the exact required dynamic range of the residue number system. This modulus set is the generalisation of the five-moduli set {2 n , 2 n − 1, 2 n + 1, 2 n+1 − 1, 2 n−1 − 1} (n even) with only a single parameter, n. The reverse converter for the new modulus set is the first ever proposed. Synthesis results obtained for the 65 nm technology for all dynamic ranges from 19 to 88 bits have shown that the state-of-the-art converters available for the five-modulus sets with a single parameter n {2 n , 2 n − 1, 2 n + 1, 2 n+1 − 1, 2 n−1 − 1} (n even) and {2 n − 1, 2 n , 2 n + 1, 2 n+1 + 1, 2 n−1 + 1} (n odd) not only introduce from 28 to 40% larger delay but also still consume more area and power than the converters proposed here.

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Section: Introductionmentioning

confidence: 99%

Design of Reverse Converters for a New Flexible RNS Five-Moduli Set $$\{ 2^k, 2^n-1, 2^n+1, 2^{n+1}-1, 2^{n-1}-1 \}$$ { 2 k , 2 n - 1 , 2 n + 1 , 2 n + 1 - 1 , 2 n - 1 - 1 } (n Even)

Patronik

Piestrak

2017

Circuits Syst Signal Process

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“…Furthermore, the intrinsic capacitance of nodes will get smaller and smaller as size of transistors and supply voltage getting lower, making the number of charges that could be stored at nodes getting smaller. This makes 6 instantaneous voltage change such as cosmos particle collision a big problem, which could destroy the device at some conditions [12]. Thus, robust technologies that has stable property when the size of transistors getting smaller is required in the near future.…”

Section: Problem and Work Statementmentioning

confidence: 99%

“…Later in the work of Wrzyszcz and Milford [6], a new partial product matrix is introduced to reduce design and hardware complexity of the previous design as well as introducing very small hardware overhead. Furthermore, their design realizes a regular VLSI layout implementation since the whole structure is almost composed by full adder and half adder only, which also dramatically optimizes the parallel computing performance, speed, and the maximum operating frequency.…”

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confidence: 99%

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A high speed low power modulo 2<sup>n</sup>+1 multiplier design using carbon-nanotube technology

Kim

Choi

2012

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Modulo 2 n +1 multiplier is one of the critical components in the area of digital signal processing, residue arithmetic, and data encryption that demand high-speed and low-power operation. In this thesis, a new circuit implementation of a high-speed low-power modulo 2 n +1 multiplier is proposed. It has three major stages: partial product generation stage, partial product reduction stage, and the final adder stage.The major technical contribition to the arts of the thesis is that the partial product reduction stage introduces a new MUX-based compressor to reduce power and increase speed. Secondly, in the final adder stage, the sparse-tree based inverted end-around-carry adder reduces the number of critical path circuit blocks. Finally, a proposed adder is implemented using both 32nm CNTFET (Carbon-Nanotube Index TermsModulo 2 n +1 Multiplier, MUX-based Compressor, Sparse-tree Adder, Carbon-Nanotube Technology

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“…We simplify the partial product (PP) matrix by exploiting special properties of the PP matrix [8] and the powers of 2 mod 2 n +1 [9]. These simplifications result in a square PP matrix with an additional correction factor, which can be shown to be a constant independent of the value of n. Consequently, the PPs can be reduced to two summands by a Dadda tree and added using an efficient mod 2 n +1 adder.…”

Section: Introductionmentioning

confidence: 98%

A low complexity modulo 2<sup>n</sup>+1 squarer design

Muralidharan

Chang

Jong

2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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Modulo 2 n +1 squaring has been used in various applications like cryptography and Fermat number transform. Arithmetic modulo 2 n +1 is also known to be the most time critical among the three residue channels in the prevalent {2 n −1, 2 n , 2 n +1} based Residue Number System (RNS). In order to speed up modulo 2 n +1 operation, the diminished-1 number representation is widely employed. However the use of diminished-1 representation results in area overhead and increased execution delay. In this paper, we present a design of modulo 2 n +1 squarer using weighted binary representation. Our synthesis results based on TSMC 0.18 m μ CMOS standard cell library indicate that the proposed squarer offers significant area and delay savings of up to 25% and 11%, respectively.

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A new modulo 2/sup a/+1 multiplier

Cited by 16 publications

References 7 publications

Design of Reverse Converters for a New Flexible RNS Five-Moduli Set $$\{ 2^k, 2^n-1, 2^n+1, 2^{n+1}-1, 2^{n-1}-1 \}$$ { 2 k , 2 n - 1 , 2 n + 1 , 2 n + 1 - 1 , 2 n - 1 - 1 } (n Even)

Design of Reverse Converters for a New Flexible RNS Five-Moduli Set $$\{ 2^k, 2^n-1, 2^n+1, 2^{n+1}-1, 2^{n-1}-1 \}$$ { 2 k , 2 n - 1 , 2 n + 1 , 2 n + 1 - 1 , 2 n - 1 - 1 } (n Even)

A high speed low power modulo 2<sup>n</sup>+1 multiplier design using carbon-nanotube technology

A low complexity modulo 2<sup>n</sup>+1 squarer design

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