A new method to fabricate sidewall insulation of TSV using a parylene protection layer

Abstract

This paper focused on the process of forming sidewall insulation of through silicon via (TSV) which was a challenging bottleneck in 3D integration technologies. In traditional way, etching silicon oxide on via bottom would reduce the thickness of sidewall insulation layer inevitably, which might lead to the failure of TSV sidewall insulation and electrical interconnection characteristic.In this paper, the parylene-C (called parylene herein) film was used to cover the silicon oxide of via in the anisotropic etching process, which prevented the silicon oxide at the sidewall from being etched. Using this method, a well sidewall insulation layer was fabricated successfully. The sidewall thickness of oxide layer gained 0.93µm, 0.49µm, and 0.40µm at the top part, middle part of the via and the via-base respectively after etching process.

Research and Development of Parylene Thin-Film Deposition and Application for Water-Proofing

“…Parylene has generally been applied as a thin film in the micrometer scale. However, thin-film deposition of parylene in the nanometer scale is now required for new applications such as the delamination layer of organic light-emitting diodes (OLED) [4], the dielectric film of through-silicon-via (TSV) [5,6] and water-proof mobile phones. Deposition chamber design and parameters must be further developed to meet nanoscale thin-film deposition uniformity requirements.…”