2012 Symposium on VLSI Technology (VLSIT) 2012
DOI: 10.1109/vlsit.2012.6242440
|View full text |Cite
|
Sign up to set email alerts
|

A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
7
0

Year Published

2014
2014
2022
2022

Publication Types

Select...
4
4
1

Relationship

0
9

Authors

Journals

citations
Cited by 17 publications
(7 citation statements)
references
References 0 publications
0
7
0
Order By: Relevance
“…Such a device was shown to exhibit superior performance with respect to a conventional vertical nanowire transistor, because of the high defectivity in the central region that plagued the performance of the latter structure. The gate stack of today's 3D NAND can be based on either a floating gate [23,[287][288][289][290][291], similar to planar NAND devices, or a charge-trap stack similar to an oxide/nitride/oxide (ONO) layer, where the charge is stored in traps within the nitride layer [10,11,22,292].…”
Section: D Nand Reliabilitymentioning
confidence: 99%
“…Such a device was shown to exhibit superior performance with respect to a conventional vertical nanowire transistor, because of the high defectivity in the central region that plagued the performance of the latter structure. The gate stack of today's 3D NAND can be based on either a floating gate [23,[287][288][289][290][291], similar to planar NAND devices, or a charge-trap stack similar to an oxide/nitride/oxide (ONO) layer, where the charge is stored in traps within the nitride layer [10,11,22,292].…”
Section: D Nand Reliabilitymentioning
confidence: 99%
“…Critical parameters for the FG cell operation are the coupling ratio between the CG and FG and FG-FG coupling. Complex structures have been proposed in order to optimize such issues [24].…”
Section: The Floating-gate Cell Architecturesmentioning
confidence: 99%
“…Another key advantage of DC-SF is the absence of FG-FG interference as the Control Gate sitting between 2 Floating Gates plays the role of electrostatic shield. As a result, this memory cells allows wide Program/Erase (P/E) threshold voltage window, which is key for multilevel storage [7]. Cross sections in Fig.…”
Section: Dual Control-gate With Surrounding Floating Gate (Dc-sf) Flamentioning
confidence: 99%