3D NAND Flash Based on Planar Cells

Abstract

Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading

“…V‐ReRAM presented in this work adopts the macaroni‐type hole structure (see Figures 1b and 3a) as in the V‐NAND flash memory and implements the nonvolatile resistive switching through the charge‐trap‐based mechanism. [ 33,34 ] Thus, the vertical and lateral charge loss can occur in V‐ReRAM as presented with blue and red arrows, respectively, in Figure 1b. Among them, the vertical charge loss can be sufficiently suppressed with the high rectification capability of the PTHT memory cell.…”

Memory technology—a primer for material scientists

“…Despite their increasing importance during the last year, they are beyond the scope of this work and the interested reader is referred to references [75,76]. The second important step is to use the third dimension to stack arrays on top of each other to increase the data density per chip area [4,6,10,74,77,78]. An even more favorable approach used for 3D NAND can be illustrated as follows: the bit-line is moved upward and the strings sharing a bit-line and GND connection are kept 'dangling' down from it.…”

“…The cells in one string are thus no longer arranged laterally next to each other and the density of strings on a given area is overall significantly increased. Another advantage that comes with this arrangement is, that the channel length and width are no longer critical dimensions in terms of scaling as the channels are arranged vertically (thus, also called 3D vertical NAND or 3D-V-NAND) and of cylindrical shape with the floating gate or charge trapping layers and the gate electrode represented by the word-planes around [10,71,77,78]. The cylindrical channels are made of poly-Si tubes (called 'macaroni cell' in literature [71]) filled into the wholes that are etched through the previously fabricated layers.…”

“…Therefore, a dense 3D memory avoiding the complicated staircase necessary for the word-line fanout of 3D NAND (see e.g. figure 7 in reference [78]) could be the envisioned target. Moreover, the density of induced domain walls can be tailored to achieve a trade-off between density and access speed.…”

Moving Processing to Data: On the Influence of Processing in Memory on Data Management

“…While Single-Layer Cells (SLC) are only able to store one single bit per cell, Multi-Layer Cells (MLC) [82] or Triple-Layer Cells (TLC) [52] can persist two or three bits per cell. Recently, even Quad-Layer Cells (QLC) [68] so-called 3D-NAND [98]. This could be done either horizontally [89] or vertically [81,82,52] to lower the production costs, increase capacities, and reduce the aggregated SSD power consumption.…”