A New LFSR Reseeding Scheme via Internal Response Feedback

Lien, Wei-Cheng; Lee, Kuen-Jong; Hsieh, Tong-Yu; Chakrabarty, Krishnendu

doi:10.1109/ats.2013.26

Cited by 3 publications

(6 citation statements)

References 13 publications

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“…The evolution of the external test set generator was crucial and established the starting point for on‐chip PGs. The literature shows techniques to assure higher test coverage, utilising test point insertion [5, 21, 22] and reseeding techniques for the LFSR [9, 10], as well as a combination of both. The strategy of applying a number of test vectors as inputs and output analyses has increased the efficiency of fault detection.…”

Section: Concatenated Techniquementioning

confidence: 99%

“…In the literature, a variety of approaches for calculation of polynomial can be found; many techniques take the way of trial‐and‐error [25], which is a very long way to find a suitable, small and full generator polynomial. In many techniques, the polynomial number of coefficients are as many or more than the number of bits present in the pattern [9, 10, 14]. In recent studies, the BM algorithm [15, 16] adapted to binary field has become a reliable calculation technique for LFSR.…”

Section: Concatenated Techniquementioning

confidence: 99%

“…Besides, LFSR has been applied for pseudorandom binary sequence generator, where the generation of pseudorandom numbers with a Gaussian distribution [8] is taken as the starting point for the PG implementation. Reseeding for higher coverage [9][10][11] is another approach, where the update of the initial value of the registers in LFSR generates more specific bit sequences for fault detection, this technique has also been utilised along with encoding of patterns for the optimisation of switching activities when unknown values are introduced in the test pattern [12,13]. [1] In continuation of PGs on chip, S max + 20, is a popular approach [14] based on reduction of the probability of linear dependencies among neighbour bits of the LFSR sequence.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

LFSR generation for high test coverage and low hardware overhead

Martínez

Khursheed

Reddy

2019

IET Computers & Digital Techniques

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Safety-critical technology rests on optimised and effective testing techniques for every embedded system involved in the equipment. Pattern generator (PG) such as linear feedback shift register (LFSR) is used for fault detection and useful for reliability and online test. This study presents an analysis of the LFSR, using a known automatic test PG (ATPG) test set. Two techniques are undertaken to target difficult-to-detect faults with their respective trade-off analysis. This is achieved using Berlekamp-Massey (BM) algorithm with optimisations to reduce area overhead. The first technique (concatenated) combines all test sets generating a single polynomial that covers complete ATPG set (baseline-C). Improvements are found in Algorithm 1 reducing polynomial size through Xs assignment. The second technique uses non-concatenated test sets and provides a group of LFSRs using BM without including any optimisation (baseline-N). This algorithm is further optimised by selecting full mapping and independent polynomial expressions. Results are generated using 32 benchmarks and 65 nm technology. The concatenated technique provides reductions on area overhead for 90.6% cases with a best case of 57 and 39% means. The remaining 9.4% of cases, non-concatenated technique provides the best reduction of 37 with 1.4% means, whilst achieving 100% test mapping in both cases.

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Section: Concatenated Techniquementioning

confidence: 99%

Section: Concatenated Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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LFSR generation for high test coverage and low hardware overhead

Martínez

Khursheed

Reddy

2019

IET Computers & Digital Techniques

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“…Several works use/assume this proposition for the selection of their characteristic polynomial. Some of these works are seed compression [15], on-line seed loading [14], [12], multiple polynomial LFSR structures [6], [10], multiple seeds to generate one or more tests [13], LFSR reseeding with additional hardware to control the LFSR behavior [8], [18], [2], [19], and reseeding targeting additional features like defect-oriented reseeding [9], [24], unmodeled faults reseeding [26] and low-power dissipation [17], [16]. What is common in all these methodologies is that the polynomial used to implement the LFSR is fixed a priori in an arbitrary manner.…”

Section: Introductionmentioning

confidence: 99%

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Acevedo

Kagaris

2016

IEEE Trans. Comput.

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In built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax + 20, where Smax is the maximum number of specified bits in any test cube of the test set. By fixing the polynomial a priori a linear system only needs to be solved to compute the required LFSR initial states (seeds) to generate the target test cubes, but the disadvantage is that the polynomial degree (length of the LFSR and seed bit size) may be too large and the fault coverage cannot be guaranteed. In this paper we address the problem of computing a polynomial of small degree directly from the given test set without having to solve multiple non-linear systems and fixing a priori the polynomial degree. The proposed method uses an adaptation of the BerlekampMassey algorithm and the Sidorenko-Bossert theorem to perform the computation. In addition, the method guarantees (by design) that all the test cubes in the given test set are generated, thereby achieving 100% coverage, which cannot be guaranteed under the "trialand-error" Smax + 20 rule. Experimental results verify the advantages that the proposed methodology offers in terms of reduced polynomial degree and 100% coverage.

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“…Researchers have proposed several methods to overcome the inefficiency in PRTG [3,8,9,14,15,[18][19][20][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

Horizontal diversity in test generation for high fault coverage

Alamgir¹,

A’ain²,

Paraman³

et al. 2018

Turk J Elec Eng & Comp Sci

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Determination of the most appropriate test set is critical for high fault coverage in testing of digital integrated circuits. Among black-box approaches, random testing is popular due to its simplicity and cost effectiveness. An extension to random testing is antirandom that improves fault detection by maximizing the distance of every subsequent test pattern from the set of previously applied test patterns. Antirandom testing uses total Hamming distance and total cartesian distance as distance metrics to maximize diversity in the testing sequence. However, the algorithm for the antirandom test set generation has two major issues. Firstly, there is no selection criteria defined when more than one test pattern candidates have the same maximum total Hamming distance and total cartesian distance. Secondly, determination of total Hamming distance and total Cartesian distance is computational intensive as it is a summation of individual Hamming distances and cartesian distances with all the previously selected test patterns. In this paper, two-dimensional Hamming distance is proposed to address the first issue. A novel concept of horizontal Hamming distance is introduced, which acts as a third criterion for test pattern selection. Fault simulations on ISCAS'85 and ISCAS'89 benchmark circuits have shown that employing horizontal Hamming distance improves the effectiveness of pure antirandom in terms of fault coverage. Additionally, an alternative method for total Hamming distance calculations is proposed to reduce the computational intensity. The proposed method avoids summation of individual Hamming distances by keeping track of number of 0s and 1s applied at each inputs. As a result, up to 90% of the computations are reduced.

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A New LFSR Reseeding Scheme via Internal Response Feedback

Cited by 3 publications

References 13 publications

LFSR generation for high test coverage and low hardware overhead

LFSR generation for high test coverage and low hardware overhead

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Horizontal diversity in test generation for high fault coverage

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