On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Abstract

In built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax + 20, where Smax is the maximum number of specified bits in any test cube of the test set. By fixing the polynomial a priori a linear system only needs to be solved to compute the required LFSR initial states (seeds) to generate the target test cubes, but the disadvantage is that the polynomial degree (length of the LFSR and seed bit size) may be too large and the fault coverage cannot be guaranteed. In this paper we address the problem of computing a polynomial of small degree directly from the given test set without having to solve multiple non-linear systems and fixing a priori the polynomial degree. The proposed method uses an adaptation of the BerlekampMassey algorithm and the Sidorenko-Bossert theorem to perform the computation. In addition, the method guarantees (by design) that all the test cubes in the given test set are generated, thereby achieving 100% coverage, which cannot be guaranteed under the "trialand-error" Smax + 20 rule. Experimental results verify the advantages that the proposed methodology offers in terms of reduced polynomial degree and 100% coverage.

LFSR generation for high test coverage and low hardware overhead

“…Other techniques for the calculation of LFSR use non-concatenated test sets [16]. In this section, an analysis of this process is provided, showing the steps involved, along with reduction techniques utilised on the polynomial set size.…”

“…The concatenation of the patterns has a linear and direct proportion to the size of the test pattern, this has a maximum iteration of O ( T ), where T is the size of the test pattern. BM algorithm complexity has a quadratic relationship with the length of the pattern O ( T 2 ), as mentioned in [16, 27].…”

“…As previously mentioned, many approaches utilise a test set organisation, where patterns remain separate, and PG generates them individually [14, 16, 23]. These techniques have been developed to improve test coverage.…”

“…[1] In continuation of PGs on chip, S max + 20, is a popular approach [14] based on reduction of the probability of linear dependencies among neighbour bits of the LFSR sequence. In recent methods, the Berlekamp-Massey (BM) algorithm [15,16] is applied as the mathematical method for accurate calculation of LFSR and the use of recurrence relation model for bit generation [17]. The use of BM provides a set of seeds for a test set, giving one seed per test pattern.…”

Reduction of Test Time using Multiple Test Control Point Insertion for 7nm Technology Node

“…But, it's always been time-taking taking process due to it checked that all cells in the design receiving signals with accuracy with timing, power, and without violation or with negligible violation. Scan design was previously implemented in [8] with linear feedback shift registers (LFSRs) in order to decompress the patterns into scan chains.…”