A new level up shifter for HVICs with high noise tolerance

Akahane, Masashi; Jonishi, Akihiro; Yamaji, Masaharu; Kanno, Hiroshi; Tanaka, Takahide; Nishio, Hiroaki; Sumida, Hitoshi

doi:10.1109/ipec.2014.6869911

Cited by 17 publications

(5 citation statements)

References 3 publications

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“…In [20], part of the parasitic current induced by power supply slewing is canceled out by two high-side dynamic currents to obtain a slew rate immunity of 40V/ns. In [21], two feedback loops from the level shifter output to input are used to cancel the slew-related influence on the input trigger signals to reach 50V/ns. Finally, Yang et al [7] present a slew rate enhancement technique to achieve 120 V/ns slew rate immunity and a propagation delay of 20 ns.…”

Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Liu

Hollis

Stark

2019

IEEE Trans. Circuits Syst. I

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Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and subns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/(µmV), which is an 1.7× improvement on the next best reported level shifter for this type of application.

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Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Liu

Hollis

Stark

2019

IEEE Trans. Circuits Syst. I

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“…The usage of discrete signal isolation transformers is also discouraged as they cannot transmit DC signals, are also prone to malfunction when subject to fastswitching CM transients and tend to become bulky when operating at low frequencies. Furthermore, integrated halfbridge drivers have the disadvantages of a low CM transient withstand capability, are not galvanically isolated and are prone to latch-up [26], [27].…”

Section: Ideal Transition Timesmentioning

confidence: 99%

Low-Jitter GaN E-HEMT Gate Driver With High Common-Mode Voltage Transient Immunity

Mauerer

Tüysüz

Kolar

2017

IEEE Trans. Ind. Electron.

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Abstract-An improved gate driver is presented which significantly lowers the output noise of high-precision switch-mode (Class-D) power amplifiers by reducing signal jitter at the output of the power stage tenfold to values below 20 ps. Gate signal jitter in power electronic converters, which introduces wideband noise to the power output, originates mainly from the signal isolators that are required to provide the galvanically isolated gate driver control signals. A low-jitter gate control signal is produced by employing a digital flip-flop, which uses a low-jitter isolated clock, to re-synchronize the jittery gate control signal. By utilizing the clock-enable input of the flip-flop, the gate driver can be rendered immune to high-speed common-mode transients, which is important as the Class-D power amplifier demonstrator system employs fast-switching GaN E-HEMT transistors, where the 400 V switching transients exceed 300 kV µs −1 . The signal to noise ratio of a sinusoidal output signal is measured at 107 dB, which is an improvement of ≈20 dB as compared to the performance of a conventional gate driver.Index Terms-Low-jitter gate driver, common-mode transient immunity (CMTI), low noise switch-mode power amplifier, wide-bandgap gallium nitride power semiconductors, signal to noise ratio (SNR)

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“…Since the level shifter can perform voltage conversion between the low-voltage domain and the high-voltage domain, MH1 and MH2 are high-voltage transistors, whose parasitic capacitance is large. The parasitic capacitance will generate a charging or discharging current when dV/dt happens, which will interfere with the level shifter's normal operation and cause errors in the driver's logic voltage of the high-voltage domain [10][11][12]. In Figure 2, it can be seen that under the action of the bootstrap capacitor C BOOT , VDDH changes with VSSH, and dVDDH/dt is approximately equal to dVSSH/dt.…”

Section: Introductionmentioning

confidence: 99%

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

Guo,

Wang,

Wang

et al. 2023

Electronics

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This paper presents a high-speed level shifter with about 500 V/ns power supply slew immunity. In this designed structure, a narrow pulse-controlled current source is adapted to accelerate the voltage conversion and reduce the power consumption. A Fast-Slewing Circuit speeds up the operation of the level shifter based on the current comparison principle. Edge detection technology is used to filter the generated voltage noise and achieve high dV/dt immunity. The proposed level shifter simulated with the 0.18 μm BCD (bipolar-CMOS-DMOS) process shows fast responses with a typical delay of 1.49 ns and 500 V/ns dV/dt immunity in the 200 V high-voltage application, which only occupies a 0.022 mm2 active area with the 0.18 μm BCD process.

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A new level up shifter for HVICs with high noise tolerance

Cited by 17 publications

References 3 publications

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Low-Jitter GaN E-HEMT Gate Driver With High Common-Mode Voltage Transient Immunity

A New Design Technique for a High-Speed and High dV/dt Immunity Floating-Voltage Level Shifter

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