Active gate driving has been demonstrated to beneficially shape switching waveforms in Si-and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limited to altering a single drive parameter once per switching event, either during or outside of the transient. This paper demonstrates a gate driver with a timing resolution and range of output resistance levels that surpass those of existing gate drivers or arbitrary waveform generators. It is shown to permit active gate driving with a bandwidth that is high enough to shape a GaN switching during the transient. The programmable gate driver has integrated high-speed memory, control logic, and multiple parallel output stages. During switching transients, the gate driver can activate a near-arbitrary sequence of pull-up or pull-down output resistances between 0.12 and 64 Ω. A hybrid of clocked and asynchronous control logic with 150-ps delay elements achieves an effective resistance update rate of 6.7 GHz during switching events. This active gate driver is evaluated in a 1-MHz bridge-leg converter using EPC2015 GaN FETs. The results show that aggressive manipulation of the gate-drive resistance at sub-nanosecond resolutions can profile gate waveforms of the GaN FET, thereby beneficially shaping the switch-node voltage waveform in the power circuit. Examples of open-loop active gate driving are demonstrated that maintain the low switching loss of constant-strength gate driving, while reducing overshoot, oscillation, and EMI-generating highfrequency spectral content.

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Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and subns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/(µmV), which is an 1.7× improvement on the next best reported level shifter for this type of application.

/ has previously been proposed as a temperature indicator for Si and SiC devices, however, the evaluation of its viability for GaN devices is challenging as known current sensors introduce significant unwanted parasitic inductance. This work presents a figure-of-eight magnetic field sensor (∞-sensor) that permits, for the first time, highbandwidth floating current sensing, with negligible insertion impedance and influence on switching performance, in highspeed GaN and SiC switching circuits. The pair of coils are connected in a way that the measurement is immune to currents outside of the sensing region. The simulated bandwidth of the sensor, taking into account the loading by the probe connected to its output, is 225 MHz. The insertion inductance is 0.2 nH, and the insertion resistance is 4.2 mΩ at 100 MHz. This sensor is used to investigate the temperature dependency of turn-on di/dt in a 650 V, 52 mΩ GaN device. It is found that both average and peak turn-on di/dt decrease with temperature. Peak di/dt appears to be the preferred temperature indicator due to its high sensitivity and linearity.

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With switching transients as fast as 100 V/ns and a low threshold voltage of 1-2 V, GaN FETs in bridge-leg topologies are potentially vulnerable to crosstalk and the resultant unwanted partial turn-on, noise interference, and increased losses. Constantstrength gate drivers for GaN FETs limit switching speed to suppress crosstalk. In this work, active gate driving is shown to permit faster switching, whilst still suppressing crosstalk. This is demonstrated in a GaN FET bridge-leg converter. The control device transients are shaped to reduce crosstalk, whilst the synchronous device's gate impedance is actively varied to increase its immunity to crosstalk. This is carried out using two 6.7-GHz active gate drivers that can dynamically vary their output resistance from 0.12 Ω to 64 Ω every 150 ps during the sub-10-ns switching transients. It is demonstrated that unwanted turn-on is suppressed without incurring undershoot and oscillation in the gate, that negative spurious gate voltages can be greatly reduced, and that oscillations in the transient drain current are damped, without incurring additional loss.

This paper deals with the separation problem of complex-valued signals in the independent component analysis (ICA) framework, where sources are linearly and instantaneously mixed. Inspired by the recently proposed reference-based contrast criteria based on kurtosis, a new contrast function is put forward by introducing the reference-based scheme to negentropy, based on which a novel fast fixed-point (FastICA) algorithm is proposed. This method is similar in spirit to the classical negentropy-based FastICA algorithm, but differs in the fact that it is much more efficient than the latter in terms of computational speed, which is significantly striking with large number of samples. Furthermore, compared with the kurtosis-based

Active gate driving has been shown to provide reduced circuit losses and improved switching waveform quality in power electronic circuits. An integrated active gate driver with 150 ps resolution has previously been shown to offer the expected benefits in GaN-based converters. However, the use of low-voltage, high-speed transistors limits its output voltage range to 5 V, too low for many emerging SiC and GaN devices. This paper introduces a series connection of two commercially available conventional drivers and an improved 5 V, 100 ps resolution active driver. The first conventional driver lifts the gate voltage from the negative hold-off voltage to just below the gate threshold voltage, the active driver performs active high-resolution control around the gate threshold, after which the second conventional driver raises the gate voltage to reach optimal Rdson values. This driver is demonstrated on a 900-V SiC MOSFET that requires a 15 V onstate gate voltage to achieve optimum Rdson. The device is switched at 50 V/ns in a 100-kHz, non-synchronous, 1:10, 300-W boost converter, with the power device switching 600 V and 5 A. It is shown that the gate voltage can be affected on a 100 ps scale, and that meaningful changes to fast power waveforms can be achieved.