A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Abstract

Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and subns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/(µmV), which is an 1.7× improvement on the next best reported level shifter for this type of application.

An Anti-Overcharged High-dV/dt-Immunity Capacitive Level Shifter with Dynamic Discharge Control for Half-Bridge GaN Driver

“…Under the condition that the CMDC do not flow into VDDH, the negative dV/dt immunity is up to 170V/ns, which is higher than that in [6]. In addition, the proposed level shifter achieves subnanosecond propagation delay and the power consumption is slightly higher than that in [9]. The FOM is 90, which is higher than that in [6], [9], but lower than that in [8].…”

“…In addition, the proposed level shifter achieves subnanosecond propagation delay and the power consumption is slightly higher than that in [9]. The FOM is 90, which is higher than that in [6], [9], but lower than that in [8]. --100 170…”

“…Compared with other works, the proposed level shifter has the highest positive dV/dt immunity, which is 300V/ns. In the proposed level shifter, the CMDC can be prevented from flowing into VDDH during negative dV/dt transitions, which cannot be realized in [8], [9]. Under the condition that the CMDC do not flow into VDDH, the negative dV/dt immunity is up to 170V/ns, which is higher than that in [6].…”

“…(2) Extracted from results in the publication. (3) From [9]: (ET•Delay)/(Process node 3 •Voltage). Unit: (pJ•ns)/(μm 3 •V)…”

A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

“…Many FHV-LSs have been proposed in the literature [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] to reduce the propagation delay. According to the structures, three topologies (Topology-I, Topology-II, and Topology-III) are summarized in Figure 1.…”