A new isolation method with boron-implanted sidewalls for controlling narrow-width effect

Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

“…In order to solve the subthreshold hump problem, many solutions have been proposed [11][12][13][14][15][16][17]. It is possible to reduce the oxide recess and corner rounding at the STI corner using an additional complicated process [11][12][13][14][15][16].…”

“…It is possible to reduce the oxide recess and corner rounding at the STI corner using an additional complicated process [11][12][13][14][15][16]. A relatively simple approach to eliminate the V T difference between the parasitic edge transistor and the main channel MOSFET is a large angle tilted ion implantation of specific dopant to the sidewalls of the trench [17]. However, the parameters of the large angle tilted ion implantation must be controlled carefully and additional photolithography is required.…”

MOSFET layout modifications for hump effect removal

“…In case of embedded Non-Volatile Memory CMOS technologies, presenting a long front-end process flow, hump effect can appear on MOSFET for analog applications. Several studies have been performed in order to understand hump effect [2,3] but it is still present on technology presenting ''thick oxide''.…”

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

“…On the other hand, the isolation technology has shifted from the conventional LOCOS to the shallow trench isolation (STI) [3] as the technology nodes have been scaled down to submicron area, and the comparison of the device reliability dependent on the isolation technologies have been reported [4][5][6]. It is expected that the STI technology may modulate the high electric fields near the channelwidth edge resulting in the reliability variation along the channel-width direction, because the narrow-width or the inverse-narrow-width effects are largely influenced by the STI process [7,8]. Until now, the reliability comparison between the buried-and the surface-channel narrow-width p-MOSFETs fabricated by STI was reported [9].…”