A new FFT architecture and chip design for motion compensation based on phase correlation

Abstract

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 p m CMOS technology and can pelform a 64 point complex forward or inverse FFTon real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7 . 8~8 mmz and dissipaires 1 W. Its pelformnce, in t e " of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

“…As we can see, the area requirement and power consumption for this work is lower than the works of Baas [9] and Hui et al [20]. On the other hand, the variable-length FFT/IFFT prototype processor can work at higher operating frequency than the works by Bidet et al [17] and Jia et al [21] and can meet various specifications in OFDM applications.…”

Synthesisable FFT cores

“…Both the Gold and Bially [5] and Bi and Jones [7] architectures take this form, albeit with considerable differences at the detailed logic level. The architecture proposed by Hui et al [8,9] also has similar properties, although, here both data, and output values are generated in reverse order, requiring circuitry to perform the data re-ordering. Each of these architectures displays various attributes in terms of performance and hardware cost.…”

“…It exhibits a 75% processor utilisation in the computational blocks and has a storage requirement of 2N complex registers. The architecture proposed by Hui et al [8,9] achieves 100% processor utilisation by using a digit-serial data organisation. In this circuit input data and processor bandwidth are matched by breaking down B bit input data words into digits B/4 bits wide.…”

“…This system operates on complex bit parallel data input and produces output results (also bit parallel) with data in reverse order. As with the system described by Hui et al [8,9], the data is internally reorganised and processed in a digit serial manner. Each processing stage therefore operates on 4 parallel digit-serial streams, each B/4 bit wide, where B is the word size.…”

“…Conventional commutators, such as those described by Swartzlander 141, do not incorporate this facility. Hui et al [8,9] showed how this blanking problem can be overcome through the use of a switch array commutator. However, this requires the use of complex control circuitry, with each half of the array controlled by separate signals.…”