A New Family of High.Performance Parallel Decimal Multipliers

Vázquez, Álvaro; Antelo, E.; Montuschi, Paolo

doi:10.1109/arith.2007.6

Cited by 107 publications

(118 citation statements)

References 13 publications

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“…A few parallel fixed-point multiplier designs have also been proposed [1,13]. The floating-point multiplier presented in this paper is based on the radix-10 fixed-point multiplier in [1] due to its highly efficient structure.…”

Section: Introductionmentioning

confidence: 99%

“…The floating-point multiplier presented in this paper is based on the radix-10 fixed-point multiplier in [1] due to its highly efficient structure. This multiplier generates a sufficient subset of multiplicand multiples and then selects all the partial-products in parallel based on the digits of the multiplier operand.…”

Section: Introductionmentioning

confidence: 99%

“…This paper presents a parallel DFP multiplier based on a parallel fixed-point multiplier [1] and a previous implementation of a DFP multiplier [15]. The novelty of the design is that it is the first parallel DFP multiplier, offering low latency, high throughput, and IEEE P754 compliance.…”

Section: Introductionmentioning

confidence: 99%

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A parallel IEEE P754 decimal floating-point multiplier

Hickmann

Krioukov

Schulte

et al. 2007

2007 25th International Conference on Computer Design

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Decimal floating-point multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper presents a fully parallel decimal floating-point multiplier compliant with the recent draft of the IEEE P754 Standard for Floating-point Arithmetic (IEEE P754). The novelty of the design is that it is the first parallel decimal floating-point multiplier offering low latency and high throughput. This design is based on a previously published parallel fixed-point decimal multiplier which uses alternate decimal digit encodings to reduce area and delay. The fixed-point design is extended to support floating-point multiplication by adding several components including exponent generation, rounding, shifting, and exception handling. Area and delay estimates are presented that show a significant latency and throughput improvement with a substantial increase in area as compared to the only published IEEE P754 compliant sequential floating-point multiplier. To the best of our knowledge, this is the first publication to present a fully parallel decimal floating-point multiplier that complies with IEEE P754.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A parallel IEEE P754 decimal floating-point multiplier

Hickmann

Krioukov

Schulte

et al. 2007

2007 25th International Conference on Computer Design

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“…3) Adder Tree where all the partial products are accumulated by using an adder tree. There are several alternatives for the accumulations of partial products as reported in [9], [10], [11]. We opted for the scheme of [9].…”

Section: E Bcd Multipliermentioning

confidence: 99%

FPGA implementation of decimal processors for hardware acceleration

2011

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Abstract-Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its execution on the CPU of the hosting computer.

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“…With the help of the ancient methodology, reciprocal algorithm has been realized by algebraic transformation of the digits to smaller ones, and the overall division has been carried out through the transformed digits; thereby, circuit complexity has been reduced substantially due to reduction in propagation delay. To carry out the transistor level implementation of decimal reciprocal unit, optimized 4221 BCD recording techniques [14,15] have been adopted in this study. The reciprocal unit is fully optimized in terms of calculations; thereby, any con guration of input could be elaborated.…”

Section: Introductionmentioning

confidence: 99%

A new algorithm for the computation of the decimals of the inverse

Saha

Kumar

2017

Scientia Iranica

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Abstract. Ancient mathematical formulae can be directly applied to the optimization of the algebraic computation. A new algorithm used to compute decimals of the inverse based on such ancient mathematics is reported in this paper. Sahayaks (auxiliary fraction) sutra has been used for the hardware implementation of the decimals of the inverse. On account of the ancient formulae, reciprocal approximation of numbers can generate \on the y" either the rst exact n decimal of inverse, n being either arbitrary large or at least 6 in almost all cases. The reported algorithm has been implemented, and functionality has been checked in T-Spice. Performance parameters, like propagation delay and dynamic switching power consumptions, are calculated through spice-spectre of 90 nm CMOS technology. The propagation delay of the resulting 4-digit reciprocal approximation algorithm was only 1:8 uS and consumed 24:7 mW power. The implementation methodology o ered substantial reduction of propagation delay and dynamic switching power consumption from its counterpart (NR) based implementation.

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A New Family of High.Performance Parallel Decimal Multipliers

Abstract: Abstract

Cited by 107 publications

References 13 publications

A parallel IEEE P754 decimal floating-point multiplier

A parallel IEEE P754 decimal floating-point multiplier

FPGA implementation of decimal processors for hardware acceleration

A new algorithm for the computation of the decimals of the inverse

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