FPGA implementation of decimal processors for hardware acceleration

Abstract

Abstract-Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its execution on the CPU of the hosting computer.

Energy efficient FPGA based hardware accelerators for financial applications

“…The architecture of the accelerator for the TELCO application is derived from the one presented in [8] with some important enhancements.…”

“…First, the accelerator of [8] could only handle small sets of data (call duration to process) because data were sent from the CPU directly to the ASP (FPGA) by using a buffer and not to the DRAM on the FPGA board. In this version of the accelerator, we designed the front-end processor, implemented on the FPGA along the ASP, to handle both the data transfer (via DMA) with the host PC, and the communication CPU-ASP (via specific instructions).…”