A parallel IEEE P754 decimal floating-point multiplier

Hickmann, Brian; Krioukov, Andrew; Schulte, Michael; Erle, M.A.

doi:10.1109/iccd.2007.4601916

Cited by 35 publications

(19 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, Op1 S i +15−Op2 S i is performed. In both cases, each result digit is in the range of [6,25], which includes a carry input into each digit. This adjustment makes carry generation simple because carries are automatically generated when a sum digit is greater than 15.…”

Section: B Additionmentioning

confidence: 99%

See 1 more Smart Citation

A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator

Akkaş

Schulte

2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

View full text Add to dashboard Cite

There is a significant demand for decimal arithmetic, especially in commercial and financial applications. Furthermore, specifications for decimal floating-point (DFP) formats and arithmetic operations have been added to the IEEE-754-2008 Standard. Hardware and software support for DFP arithmetic operations have been investigated, especially in the last decade. This paper presents a novel DFP fused multiply-add (DFP-FMA) unit and a new decimal leading-zero anticipator (LZA). The DFP-FMA design uses a previously published parallel fixedpoint decimal multiplier for multiplication and a Kogge-Stone parallel prefix adder for decimal addition. The DFP-FMA unit is synthesized using LSI Logic's gflxp 65-nm CMOS standard cell library. Synthesis results show that a 1.07-ns cycle time is obtained when the unit is synthesized with five pipeline stages. Furthermore, a new decimal LZA presented in this paper predicts zero-digit positions exactly and reduces the latency of the DFP-FMA operation. The correctness of the new decimal LZA is fully tested.

show abstract

Section: B Additionmentioning

confidence: 99%

“…IBM's POWER6, z9, and z10 microprocessors support DFP arithmetic. Furthermore, several hardware designs for DFP arithmetic have been developed to speed up DFP arithmetic operations [5], [6], [7], [8], [9]. Such designs support DFP addition, multiplication, and division operations.…”

Section: Introductionmentioning

confidence: 99%

A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator

Akkaş

Schulte

2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

View full text Add to dashboard Cite

show abstract

“…The generation of decimal partial products is based on the techniques described in [8,3]. First of all, decimal digits of A are represented in BCD-4221 (4221) to prevent the corrections previously mentioned.…”

Section: An Overview Of Bcd Multipliermentioning

confidence: 99%

Implementation of a fully pipelined BCD multiplier in FPGA

Guardia

2012

2012 VIII Southern Conference on Programmable Logic

View full text Add to dashboard Cite

Decimal multiplication is one of the most frequently used operations in financial, scientific, commercial and internetbased applications. This paper presents an efficient implementation of a fully pipelined decimal multiplier designed with Carry Save Addition and coded into a reduced group of BCD-4221. This design is based on multiplier operands recoded in Signed-Digit radix-10, a simplified partial products generator, and decimal adders. A variety of multipliers architectures are processed on a Virtex-6 FPGA device. Several assessments are carried out in various N by M multiplications and their respective synthesis results show slightly optimistic figures in terms of area and delay in regard to some previously published works.

show abstract

“…For efficient implementation of the floating point multiplier Vedic multiplication is used for calculating mantissa part [7,8]. The format for representing 32-bit and 64-bit floating point numbers are provided by the IEEE 754 standard [9,10]. IEEE 754 uses a fixed number of bits for representing the 32-bit floating point number.…”

Section: Introductionmentioning

confidence: 99%

Design and Synthesis of Single Precision Floating Point Division based on Newton-Raphson Algorithm on FPGA

Singh

Sasamal

2016

MATEC Web of Conferences

View full text Add to dashboard Cite

Abstract. This paper describes a single precision floating point division based on Newton-Raphson computational division algorithm. The Newton-Raphson computational algorithm is implemented using 32-bit floating point multiplier and subtractor. The salient feature of this proposed design is that the module for computing mantissa in 32-floating point multiplier is designed using a 24-bit Vedic multiplication (Urdhva-triyakbhyam-sutra) technique. 32-bit floating point multiplier, designed using Vedic multiplication technique, yields a higher computational speed, hence, is efficiently used in floating point divider. Another important feature is the efficient use of device utilization parameters and reduced power consumption. An advantage of the Newton-Raphson algorithm is the higher versatility and precision. For representing 32-bit floating point numbers, IEEE 754 standard format is used. ISim simulator is used for simulation. The proposed floating point divider is designed using Verilog Hardware Description Language (HDL) and is verified on Xilinx Spartan 6 SP605 Evaluation Platform FPGA.

show abstract

A parallel IEEE P754 decimal floating-point multiplier

Cited by 35 publications

References 13 publications

A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator

A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator

Implementation of a fully pipelined BCD multiplier in FPGA

Design and Synthesis of Single Precision Floating Point Division based on Newton-Raphson Algorithm on FPGA

Contact Info

Product

Resources

About