A New DLL-Based Approach for All-Digital Multiphase Clock Generation

Chung, Ching-Che; Lee, Chen‐Yi

doi:10.1109/jssc.2003.822890

Cited by 55 publications

(17 citation statements)

References 13 publications

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“…In the earlier delay-locked loop (DLL)-based multiphase clock generation approach [11], the TDC enables a delay line locked to a single clock period , giving a in each delay stage. In a high-speed cell-based DLL design, however, maintaining such a short delay and a high resolution simultaneously is difficult.…”

Section: Ptcgmentioning

confidence: 99%

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

Chung

Lee

2008

IEEE Trans. Circuits Syst. II

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Abstract-This work addresses power reduction and performance improvement for wireless orthogonal frequency-division multiplexing (OFDM) systems using a dynamic sample-timing controller (DSTC) and phase-tunable clock generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the Nyquist rate (or higher), to reduce the extra power consumed in high-rate operations. The proposed PTCG circuits provide the desired clock phase for optimum sampling to improve system performance. Both the DSTC and the PTCG are evaluated in a multibandt OFDM (MB-OFDM) ultra-wide-band system. Simulation results indicate that the overall system performance is improved by 1.7-dB signal-to-noise ratio at a packet error rate of 8% and the total baseband power is reduced by 40%.Index Terms-Dynamic sample-timing controller (DSTC), orthogonal frequency-division multiplexing (OFDM), phase-tunable clock generator (PTCG), synchronization, ultra-wide-band.

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Section: Ptcgmentioning

confidence: 99%

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

Chung

Lee

2008

IEEE Trans. Circuits Syst. II

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“…However, the antifalse-lock algorithm requires a complicated logic with less design flexibility. The works in [7] and [8] use a time-to-digital converter (TDC) scheme to measure a clock period for an antiharmonic lock. Although the TDC selects a proper delay range according to the input frequency, the processing block for estimating a single period and the buffer chain with TDC require large chip area and power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…Although the TDC selects a proper delay range according to the input frequency, the processing block for estimating a single period and the buffer chain with TDC require large chip area and power consumption. In addition, the work in [8] needs an external reset signal for correcting the locking process. The work in [9] can correct the PD stuck false lock but should wait until the stuck false lock falls into a harmonic-lock condition.…”

Section: Introductionmentioning

confidence: 99%

A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Moon

Kong

Ryu

et al. 2014

IEEE Trans. Circuits Syst. II

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This brief describes a wide-range operating falselock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15-μm 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.Index Terms-Complementary metal-oxide-semiconductor (CMOS), delay-locked loop (DLL), display interface, false lock, harmonic lock.

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“…For multi-phase clock generation, delay-locked loops (DLLs) are often used [3]. Other than a DLL, a shift register can also be used to generate multi-phase clocks [2].…”

Section: Introductionmentioning

confidence: 99%

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

Gao

Klumperink

Nauta

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.

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A New DLL-Based Approach for All-Digital Multiphase Clock Generation

Cited by 55 publications

References 13 publications

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

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