This brief describes a wide-range operating falselock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15-μm 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.Index Terms-Complementary metal-oxide-semiconductor (CMOS), delay-locked loop (DLL), display interface, false lock, harmonic lock.
This paper presents a precise time-difference repetition technique to enhance the timing accuracy in repetition based time-to-digital converters (TDC). In the proposed scheme, any delay mismatches during timing difference repetition process can be removed. The proposed circuit could be used for multi-step TDC, delta-sigma TDC, and SAR-type TDC. The proposed scheme was designed and simulated with a 65-nm CMOS process. The proposed circuit shows a delay variation of about 100 fs in the presence of device mismatches, which is much less than that of conventional approaches. The input time range and the conversion rate is 480 ps and 100 Msps if applied to a 2-step TDC, respectively.
This paper describes a modified binary phase detector (Bang-Bang phase detector-BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu 0.13μm CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.
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