A New DAC Mismatch Shaping Technique for Sigma–Delta Modulators

Aboudina, Mohamed M.; Razavi, Behzad

doi:10.1109/tcsii.2010.2083172

Cited by 12 publications

(6 citation statements)

References 11 publications

(20 reference statements)

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“…The non-linearities in the DAC are one of the critical bottlenecks for the overall performance of the ADC. In order to cope with these non-linearities, various dynamic element matching (DEM) techniques have been used, for example, [76][77][78][79][80][81][82][83][84][85][86][87][88][89]. A disadvantage of the DEM is that size and power consumption grow exponentially with the increased word length and higher resolution of the digital feedback signal.…”

Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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“…1 (a). Here, analog differentiators are inserted in the paths of DACs as [3], however, instead of using digital accumulators, an analog integrator is employed in the loop filter, and meanwhile, a digital differentiator is used before the output of SDM. Since the digital differentiator is out of the sigma-delta loop, it will not cause any delay in the SDM loop.…”

Section: Proposed Dac Mismatch Shaping Structurementioning

confidence: 99%

“…2 (b), the quantizer is a 4-bit Flash ADC which reference voltage has a 0.5 times scaling to realize the 2 times gain of the quantizer's input path. The two branches of feedback DACs are realized by capacitors with series switch as [3]. The integrating operation is performed in phase Φ 1 , and a half cycle Φ 2 is left for quantization and the following digital operation.…”

Section: Proposed Topologymentioning

confidence: 99%

“…Dynamic element matching (DEM) [1] especially the data-weighed averaging algorithm (DWA) is the most widely used method to calibrate this error. Since for low-pass SDMs DWA mismatch shaping function of DAC error is (1 − z −1 ) which is a first-order shaping [2], it can also be realized in analog domain [3] at the cost of an extra digital integrator (accumulator) inserted in SDM loop. Although the accumulator presents smaller feedback logic delay than DWA, the more bits of the DAC, the larger delay will appear.…”

Section: Introductionmentioning

confidence: 99%

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Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM

Wang

Jia

et al. 2011

IEICE Electron. Express

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This paper presents a novel technique to shape feedback DAC mismatch without any extra digital elements inside the sigmadelta loop by inserting an analog integrator and an out-of-loop digital differentiator. To lower power dissipation, a novel triple integrator with low capacitor mismatch sensitivity of the delay paths is proposed. As a result, the SDM with three integrators is realized by only one OTA. The proposed topology, simulated at transistor level on 0.13 µm CMOS process, achieves 98.4 dB SNDR with 100 kHz bandwidth and 1.2 mW power dissipation from a single 1.2 V supply voltage. Its specification satisfies the GSM requirements.

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“…To further save power, charge-pump based integrators [12] and charge compensation [13] were suggested to relax the slew rate and settling requirements of the OTAs. However, the drawback of all these techniques is the critical timing required for the quantization and the dynamic element matching (DEM) circuitry [14], [15]. The stability of the loop requires that the quantizer and the DEM operate in the non-overlapping clock intervals.…”

Section: Introductionmentioning

confidence: 99%

Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays

Meng

Zhang

et al. 2015

IEEE Trans. Circuits Syst. I

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This paper presents several novel low-power low-distortion modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTA's requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single-and double-sampled third-order modulators with and without noise coupling were analyzed and simulated.

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A New DAC Mismatch Shaping Technique for Sigma–Delta Modulators

Cited by 12 publications

References 11 publications

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM

Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays

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