A new cycle test system emulating inductive switching waveforms

Glavanovics, Michael; Köck, Helmut; Eder, Heinrich; Kosel, V.; Smorodin, T.

doi:10.1109/epe.2007.4417742

Cited by 15 publications

(11 citation statements)

References 4 publications

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“…Three parameters (V ds , I load , R dson ) are acquired in situ during a stress test run for each DUT. A similar centralized architecture has also been used for the test system described in [8] in which the inductive clamping behavior of power MOSFETs after turn off is analyzed.…”

Section: Discussion Of State-of-artmentioning

confidence: 99%

“…Therefore, repetitive inductive clamping stress tests are of interest, too. In [8], a test system designed for such purpose is introduced which again has a centralized architecture. For the definition of stress conditions, passive inductive loads are replaced by active driving circuits which provide the DUTs with current pulses of arbitrary shape.…”

Section: Inductive Load Clampingmentioning

confidence: 99%

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Modular test system architecture for device, circuit and system level reliability testing

Sleik

Glavanovics

Einspieler

et al. 2016

2016 IEEE Applied Power Electronics Conference and Exposition (APEC)

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Reliability stress testing of power semiconductors requires significant development effort for a test apparatus to provide the required functionality. This paper presents a modular test system architecture which focuses on flexibility, reusability and adaptability to future test requirements. Different types of tests for different devices in application circuit configuration can be implemented based on the same modular test system concept. Vital parameters of the device under test (DUT) can be acquired in situ during the running stress test. This enables to collect drift data of this parameters. The control and data acquisition parts of the test system are separated from the actual test circuit. With this physical separation, the same control part can be used for different types of tests. Experimental results of a prototype test system are provided.

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Section: Discussion Of State-of-artmentioning

confidence: 99%

Section: Inductive Load Clampingmentioning

confidence: 99%

Modular test system architecture for device, circuit and system level reliability testing

Sleik

Glavanovics

Einspieler

et al. 2016

2016 IEEE Applied Power Electronics Conference and Exposition (APEC)

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“…The data of interest contain partially censored lifetime data from five different types of smart power switch (SPS) (device A, B, C, D, and E) obtained under 65 different electrical and thermal stress conditions; see Table . The observed lifetime (discussed in Section ) is the result of accelerated repetitive stress tests performed by a cycle stress test system . The induced stress is characterized by predefined electrical test settings (discussed in Section ) and resulting electro‐thermal as well as thermo‐mechanical effects (discussed in Sections and ).…”

Section: Data and Challengesmentioning

confidence: 99%

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

2015

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In this article, Bayesian networks are used to model semiconductor lifetime data obtained from a cyclic stress test system. The data of interest are a mixture of log-normal distributions, representing two dominant physical failure mechanisms. Moreover, the data can be censored due to limited test resources. For a better understanding of the complex lifetime behavior, interactions between test settings, geometric designs, material properties, and physical parameters of the semiconductor device are modeled by a Bayesian network. Statistical toolboxes in MATLAB® have been extended and applied to find the best structure of the Bayesian network and to perform parameter learning. Due to censored observations Markov chain Monte Carlo (MCMC) simulations are employed to determine the posterior distributions. For model selection the automatic relevance determination (ARD) algorithm and goodness-of-fit criteria such as marginal likelihoods, Bayes factors, posterior predictive density distributions, and sum of squared errors of prediction (SSEP) are applied and evaluated. The results indicate that the application of Bayesian networks to semiconductor reliability provides useful information about the interactions between the significant covariates and serves as a reliable alternative to currently applied methods.

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“…As devices under test may fail in a short circuit as well as in an open (high ohmic) condition, detection of both failure modes by voltage and current measurements during individual test pulses has been implemented in the switching test system [5].…”

Section: Dmos-stress Setupmentioning

confidence: 99%

Power-cycling of DMOS-switches triggers thermo-mechanical failure mechanisms

Smorodin

Stecher

Wilde

et al. 2007

ESSDERC 2007 - 37th European Solid State Device Research Conference

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Figure 1. Circuit-diagram of a low-side switch driving an inductive load. The relationship between voltage, current and temperature is displayed at the right side. The high power dissipation during the switchoff causes a sharp temperature rise. Figure 2. SEM-image of a DMOS-switch with aluminum in the power metallization after exposure to power-cycle stress. A massive buckling of the metallization and passivation cracks are visible, as well as aluminum extrusions at the broken edges Abstract-In this article the failure behavior of DMOSswitches under power-cycle stress is shown to be dominated by thermo-mechanical deformation of the metallization. The failure evolves without a significant influence from electromigration stress.

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A new cycle test system emulating inductive switching waveforms

Cited by 15 publications

References 4 publications

Modular test system architecture for device, circuit and system level reliability testing

Modular test system architecture for device, circuit and system level reliability testing

Bayesian Network Model with Application to Smart Power Semiconductor Lifetime Data

Power-cycling of DMOS-switches triggers thermo-mechanical failure mechanisms

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