11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)
DOI: 10.1109/ispsd.1999.764055
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A new concept for the lateral DMOS transistor for smart power IC's

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Cited by 22 publications
(8 citation statements)
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“…A more uniform vertical electric field is obtained and V L2 in Fig. 2(a) is enhanced, and therefore, the V B is increased from 91 V to 133 V. Moreover, the maximum doping concentration in the n-drift region can be increased from 1.9 Â 10 14 cm À3 for the device without a p-silicon to 1.6 Â 10 16 cm À3 for the device with a p-silicon, which means a lower R on,sp at the [8] [4] [6] [2] ideal Si limit [22] Ron,sp (m cm [11] 107 0.96 11.9 ERT SOI pLDMOS in [16] 329 13. At the on-state, the introduced interface buried n + layer (low-resistance) for BID MOSFET shortens the distance between the channel and n + region at drain side compared with the conventional trench MOSFET, which will lead to a lower R on,sp just as shown in the inset of Fig.…”
Section: Parameter Valuementioning
confidence: 99%
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“…A more uniform vertical electric field is obtained and V L2 in Fig. 2(a) is enhanced, and therefore, the V B is increased from 91 V to 133 V. Moreover, the maximum doping concentration in the n-drift region can be increased from 1.9 Â 10 14 cm À3 for the device without a p-silicon to 1.6 Â 10 16 cm À3 for the device with a p-silicon, which means a lower R on,sp at the [8] [4] [6] [2] ideal Si limit [22] Ron,sp (m cm [11] 107 0.96 11.9 ERT SOI pLDMOS in [16] 329 13. At the on-state, the introduced interface buried n + layer (low-resistance) for BID MOSFET shortens the distance between the channel and n + region at drain side compared with the conventional trench MOSFET, which will lead to a lower R on,sp just as shown in the inset of Fig.…”
Section: Parameter Valuementioning
confidence: 99%
“…Power MOSFETs with a trench-based technology have been shown to reduce R on,sp because of the reduced cell pitch [1,2]. Fujishima and Salama investigated a trench lateral power MOSFET (TLPM) with a trench bottom drain contact with the simulated performances of V B = 80V and R on,sp = 0.8 mX cm 2 [3].…”
Section: Introductionmentioning
confidence: 99%
“…To make LDMOS more efficient, a kind of trench LDMOS (T-LDMOS) is developed [2]- [3]. It uses a deep and narrow trench filled with dielectric to sustain most of the surface voltage.…”
Section: Introductionmentioning
confidence: 99%
“…These trench depths are compatible with the space charge extension arising in reverse biased junction for substrate doping in the range of 2.1013 ~m -~, corresponding to an 0-7803-6384-1 1001$10.00 Q 2000 IEEE 86 ideal breakdown voltage in bulk of 6 kV and a maximal plane space charge extension of 620 pm. A first proposal was to use the trench itself to sustain the largest part as possible of the electric field [3]. For low voltage range (<80 V), filling the trench with oxide is efficient.…”
Section: Principle Of Trench Termination Technique :T3mentioning
confidence: 99%
“…We want to emphasize the fact that, contrarily to the low voltage application [3], the material filling the trench does not have any role in electric field repartition; this role is devoted to the JTE alone.…”
Section: Designs Rules Of Jte T3mentioning
confidence: 99%