Trench termination technique with vertical JTE for 6 kV devices

Dragomirescu, Daniela; Charitat, G.

doi:10.1109/bipol.2000.886179

Cited by 6 publications

(3 citation statements)

References 6 publications

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“…The implant angel is determined by arctan (D t /W t ). Alternatively, the p-drift can be fabricated by diffusion process for the large D t /W t , as discussed in [27]. For W t = 4 μm and D t = 8 μm, the implant angle is around 25°.…”

Section: B Bg Effectmentioning

confidence: 99%

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Zhou

Luo

et al. 2014

IEEE Trans. Electron Devices

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A low specific ON-resistance (R ON,sp ) silicon-oninsulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFFstate, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low R ON,SP and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and R ON,SP . Compared with the p-top SOI pLDMOS, the proposed device reduces the R ON,SP by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail.Index Terms-Back gate (BG), breakdown voltage (BV), p-channel LDMOS (pLDMOS), reduced surface field (RESURF), specific ON-resistance.

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Section: B Bg Effectmentioning

confidence: 99%

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Zhou

Luo

et al. 2014

IEEE Trans. Electron Devices

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“…The hole-bypassing gate configuration can also increase its immunity against the latch-up effect. However, the simple oxide-filled trench is not enough to protect the junction from higher voltage ( >80 V) [17]. It increases the complexity of technology for adding an emitter-side field plate (EFP) [12] to solve this problem.…”

Section: Introductionmentioning

confidence: 99%

Small‐sized silicon‐on‐insulator lateral insulated gate bipolar transistor for larger forward bias safe operating area and lower turnoff energy

Zhang

Luo

et al. 2013

Micro & Nano Letters

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This Letter presents a novel small-sized lateral insulated gate bipolar transistor on silicon-on-insulator substrate (SOI-LIGBT), which features a lowly doped p-type pillar alongside the oxide trench in the drift region. The variation in vertical doping termination technology is also proposed for the first time. The p-pillar layer leads to electric field reshaping in the y-direction, and homogenises current flow lines under the gate and cathode. It results in a very wide forward bias safe operating area (FBSOA) for the proposed SOI-LIGBT, which is obviously improved by over 50% compared with the deep-oxide trench SOI-LIGBT (DT SOI-LIGBT). Moreover, at the same forward voltage drop of 1 V, the turnoff energy loss for the proposed SOI-LIGBT is reduced by 28.5 and 81.2% compared with those of DT SOI-LIGBT and the conventional SOI-LIGBT, respectively.

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“…Recently, several junction terminations with a deep trench have been reported [8], [9], [10]. The T 3 JTE [8], the concave junction employing deep trench [9] and the deep trench junction termination using inductive coupled plasma reactive ion etching (ICP-RIE) [10] required a deep silicon etching (usually several tens or several hundreds microns) in order to decrease the junction termination area and increase the breakdown voltage. The T 3 JTE was not experimentally demonstrated.…”

Section: Introductionmentioning

confidence: 99%

A new junction termination technique: The Deep Trench Termination (DT<sup>2</sup>)

Théolier

Mahfoz-Kotb

Isoird

et al. 2009

2009 21st International Symposium on Power Semiconductor Devices &Amp; IC's

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Numerous techniques have been used to improve the voltage handling capability of high voltage power devices with the aim to obtain the breakdown of a plane junction. In this work, a new concept of low cost, low surface and high efficiency junction termination for power devices is presented and experimentally validated. This termination is based on a large and deep trench filled by BCB (BenzoCycloButene) associated to a field plate. Simulation results show the important impact of trench design and field plate width on termination performances. The experimental breakdown voltage of this DeepTrench Termination (DT 2 ) is close to 1300 Volts: this value validates not only the concept of the DT 2 but also the choice of the BCB as a good dielectric material for this termination.I.

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Trench termination technique with vertical JTE for 6 kV devices

Abstract: A new termination technique using deep trenches and vertical JTE is reported. The device breakdown voltage is increased to almost the ideal value and the consumed Silicon area is much lower than other solutions.

Cited by 6 publications

References 6 publications

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Small‐sized silicon‐on‐insulator lateral insulated gate bipolar transistor for larger forward bias safe operating area and lower turnoff energy

A new junction termination technique: The Deep Trench Termination (DT<sup>2</sup>)

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