A New Characterization Method for Delay and Power Dissipation of Standard Library Cells

Abstract

A simplified method for characterization of standard library cells based on the linear delay model is presented in this paper. The linear model is chosen as it allows rapid characterization with a modest number of simulations, while achieving acceptable accuracy. All the parameters of cell delays are defined as 50%-to-50% delays, as distinguished from 50%-to-threshold or threshold-to-50% often used in commercial tools. We found that the 50%-to-50% definition of delays is more consistent and leads to closed-form formula. A subset of library cells in a 0.25 μm technology was characterized using the proposed technique. A test circuit was subsequently generated and simulated to determine the accuracy of the proposed characterization method. SPICE simulations on the test circuit show that the timing estimations obtained through the proposed method is accurate to within 5.6%, and the power estimation was accurate to 4.2%, ignoring parasitics on interconnections.

Co-optimization of Performance and Power in a Superscalar Processor Design

“…We validated this model by comparing its predicted power consumptions with simulation over the same benchmarks using Sim-Wattch [4] and the results are on average within 10.9% accuracy. The average power consumption obtained by our model agrees with the measured result reported by Synopsys Power Compiler with a power library from Virginia Tech [12]. Our average result also agrees with analytical outcome of the Berkeley Advanced Chip Performance Calculator (BACPAC) [13].…”

“…The power consumption is close to the averaged analytical power of 27.38 watts. Using the same V dd , clock frequency and a 0.25μm technology based power library by Sulistyo and Ha [12], we also obtained a total power of 32.1 watts reported by the Synopsys Power Compiler. for a similar RISC processor design in the scale.…”

New Self-Checking Booth Multipliers

“…The multiplier was implemented in VHDL, tested by ModelSim and mapped to the vtvtlib25 cmos library (Sulistyo andHa, 2002, 2003) by the Synopsis design compiler. Optimization was performed for the area and delay, such that all multipliers have almost the same delay.…”

High Rate Data Synchronization in GALS SoCs

“…The circuits of Sections VI-F-VI-H were synthesized using Petrify [30], converted to VHDL, synthesized by the synopsys design compiler using 0.35-and 0.25-m CMOS libraries [31], [32], and verified by gate level simulations with wire-load model delays (SDF). Table III lists the results for the three controllers.…”