A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

Jeong, Hyemin; Song, Ki–Whan; Park, Il Han; Kim, Tae-Hun; Lee, Yeun Seung; Kim, Seong-Goo; Seo, Jihoon; Cho, Kyoungyong; Lee, Kang Yoon; Shin, Hyungcheol; Lee, Jong Duk; Park, Byung‐Gook

doi:10.1109/tnano.2007.893575

Cited by 41 publications

(19 citation statements)

References 5 publications

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“…In both the silicon and poly-Si 1T-DRAMs, the sensing margin decreases in proportion to T body. However, the acceptable sensing margin is about 3 uA [4], and the sensing margin of silicon devices are smaller than 3uA regardless of T body . For the 50 nm and 30 nm T body values, the sensing margin of poly-Si 1T-DRAM decreases only 30%, while that of silicon decreases by 90%, as shown Table 2.…”

Section: Write "1"mentioning

confidence: 99%

“…Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) has reached its scaling limit due to the difficulty of miniaturizing capacitors. Therefore, capacitor-less one-transistor dynamic random-access memory (1T-DRAM), which does not need complicated capacitor fabrication, has been studied as a possible replacement for 1T-1C DRAM [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. 1T-DRAM can be densely integrated because it has a small 4F 2 cell size with a silicon-on-insulator (SOI) transistor as its basic structure.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

et al. 2020

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Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

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Section: Write "1"mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

et al. 2020

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“…As a result, they have dramatically higher Read "1" current hence sensing margin. Recently developed current sense amplifiers are able to detect a current difference down to 2~3uA [3]. In this work, retention time is defined as the time for the sensing margin to drop below 20uA/um [6].…”

Section: Retention Timementioning

confidence: 99%

“…Thus, there have been many efforts to investigate improved cell designs. Multiple-gate cell designs have been proposed [2,3]. Recently, the capacitorless DRAM Generation 2 (BJT-based) cell design was developed to improve sensing margin [4].…”

Section: Introductionmentioning

confidence: 99%

Convex Channel Design for Improved Capacitorless DRAM Retention Time

Cho

Shin

Liu

2009

2009 International Conference on Simulation of Semiconductor Processes and Devices

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Abstract-A convex channel surface with Si 0.8 Ge 0.2 is proposed to enhance the retention time of a capacitorless DRAM Generation 2 type of capacitorless DRAM cell. This structure provides a physical well together with an electrostatic barrier to more effectively store holes and thereby achieve larger sensing margin as well as retention time. The advantages of this new cell design as compared with the planar cell design are assessed via twodimensional device simulations. The results indicate that the convex heterojunction channel design is very promising for future capacitorless DRAM.

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“…The current I 1 , across M 2 in read "1" mode, is about 6.4×10 -5 A, while the current I 0 , across M 2 in read "0" mode, is about 3.7×10 -8 A. The ratio between the two is about 1756, much larger than the current ratio (I 1 /I 0 ) in the DRAM cell based on FBC [1]- [6]. Fig.5 and Fig.6 are the simulation results for access time of the cell.…”

mentioning

confidence: 99%

A Novel Capacitor-less 2-T SOI DRAM Cell

Zhang

Shao

2007

2007 International Semiconductor Device Research Symposium

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The capacitor in conventional 1T/1C DRAM cell accounts for large area and can hardly be realized by SOI technology. Several kinds of capacitor-less DRAM cell have been proposed and developed [1]- [7]. Most of them are realized based on Floating-body cell (FBC) [1]-[6], however, these cells rely on the mechanism of impact ionization to write the "1" state and need relative high voltage. M. Terauchi [7] has proposed a capacitor-less DRAM cell based on MOSFET and parasitical JFET. This cell can operate in low voltage, but needs super shallow junction, which is difficult to realize in process and not suitable for scaling down. In this work, a novel capacitorless two-transistor (2-T) SOI DRAM cell is proposed for the first time.

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A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

Cited by 41 publications

References 5 publications

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Convex Channel Design for Improved Capacitorless DRAM Retention Time

A Novel Capacitor-less 2-T SOI DRAM Cell

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