A New Architecture for High-Density High-Performance SGT nor Flash Memory

Kadowaki, Takuya; Yamakawa, Y.; Nakamura, Hiroki; Kimura, Yasuhiro; Niwano, Michio; Masuoka, F.

doi:10.1109/tcsii.2007.916672

Cited by 5 publications

(5 citation statements)

References 13 publications

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“…The F-N tunneling occurs when the applied electric field between the substrate and the CG is sufficiently large to overcome the potential barrier if the FG is charged. F-N tunneling is widely employed in actual flash memories since the voltage required for the write operation is lower than in HEI-based memory cells [33,34,35]. …”

Section: Technical Backgroundmentioning

confidence: 99%

“…Regarding the physical size, the results found in [35] showed that NOR flash memory is scaled down to 50 nm with a cell size of 6.6 F 2 . Considering the same F as the one used for NAND flash cell size estimation—14 nm—the cell area of the NOR flash memory is 1293 nm 2 , which is approximately two times more than for NAND flash.…”

Section: Technical Backgroundmentioning

confidence: 99%

See 1 more Smart Citation

Conceptual Design of a Nano-Networking Device

Canovas-Carrasco

García-Sánchez

García‐Sánchez

et al. 2016

Sensors

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Nanotechnology is an emerging scientific area whose advances, among many others, have a positive direct impact on the miniaturization of electronics. This unique technology enables the possibility to design and build electronic components as well as complete devices (called nanomachines or nanodevices) at the nano scale. A nanodevice is expected to be an essential element able to operate in a nanonetwork, where a huge number of them would coordinate to acquire data, process the information gathered, and wirelessly transmit those data to end-points providing innovative services in many key scenarios, such as the human body or the environment. This paper is aimed at studying the feasibility of this type of device by carefully examining their main component parts, namely the nanoprocessor, nanomemory, nanoantenna, and nanogenerator. To this end, a thorough state-of-the-art review is conveyed to discuss, substantiate, and select the most suitable current technology (commercial or pre-commercial) for each component. Then, we further contribute by developing a complete conceptual nanodevice layout taking into consideration its ultra-small size (similar to a blood cell) and its very restricted capabilities (e.g., processing, memory storage, telecommunication, and energy management). The required resources as well as the power consumption are realistically estimated.

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Section: Technical Backgroundmentioning

confidence: 99%

Section: Technical Backgroundmentioning

confidence: 99%

Conceptual Design of a Nano-Networking Device

Canovas-Carrasco

García-Sánchez

García‐Sánchez

et al. 2016

Sensors

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“…In either case, these blocks are independent of each other and the good blocks can be affected nothing but jumping over the bad ones [3] . There are some major work in the bad blocks management .To begin with, we should detect the block mark of every block in the chip and build up the block mapping table.…”

Section: The Bad Management Of Nandflashmentioning

confidence: 99%

NAND Flash Bad Block Management Research Based On FPGA

Wu¹,

Hu²,

Wu³

2015

Proceedings of the 2015 International Conference on Applied Science and Engineering Innovation

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Abstract. For the requirement of the stability in large-capacity data storage, this paper proposes a management method of bad block based on setting up block address mapping table in the interior of FPGA. While operating the NAND Flash , we can take advantage of the mapping tables to shield inherent bad blocks and new produced blocks .The research proved that the method can avoid the operation of bad blocks efficiently and improve the reliability of data shortage greatly.

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“…It also indicates that the multiple-gate (MG) MOSFETs with the strong field confinement, prominent volume conduction, and high packing density can be the promising candidates for the future CMOS application. The novel structures for the surrounding-gate (SRG) MOSFETs with the high performance and scalability can be used for the memory DRAM cell [1]. To utilize this device for the memory cell application, it is mandatory to develop a feasible model.…”

Section: Introductionmentioning

confidence: 99%

A new interface-trapped-charge-degraded subthreshold current model for cylindrical, surrounding-gate (CSRG) MOSFETs

Chiang

Gao

Liu

et al. 2014

2014 International Symposium on Next-Generation Electronics (ISNE)

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IntroductionITRS has revealed that the implantation of non-classical CMOS structures are needed to overcome the difficult challenges when the semiconductor technology node is below 16nm. It also indicates that the multiple-gate (MG) MOSFETs with the strong field confinement, prominent volume conduction, and high packing density can be the promising candidates for the future CMOS application. The novel structures for the surrounding-gate (SRG) MOSFETs with the high performance and scalability can be used for the memory DRAM cell [1]. To utilize this device for the memory cell application, it is mandatory to develop a feasible model. Although a numerous of literatures have modeled the drain current for the MG devices [2] [3], there are no investigations on the subthreshold current model for the cylindrical, surrounding-gate (CSRG) MOSFETs with the interface trapped charges. In this paper, by accounting for the effects of interface trapped charges on the flat-band voltage, we propose a compact sub-threshold current model for the CSRG MOSFETs with the interface trapped charges based on the scaling equation and drift-diffusion approach. The proposed model explicitly illustrates how the interface trapped charges with different polarities, damaged zone lengths, gate oxide, and silicon body thicknesses affect the subthreshold current degradation. The model can be used to explore the hot-carrier-induced sub-threshold current degradation for the CSRG MOSFET for its memory device application.

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A New Architecture for High-Density High-Performance SGT nor Flash Memory

Cited by 5 publications

References 13 publications

Conceptual Design of a Nano-Networking Device

Conceptual Design of a Nano-Networking Device

NAND Flash Bad Block Management Research Based On FPGA

A new interface-trapped-charge-degraded subthreshold current model for cylindrical, surrounding-gate (CSRG) MOSFETs

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