A network on chip architecture and design methodology

Kumar, Shashi; Jantsch, Axel; Soininen, Juha-Pekka; Forsell, Martti; Millberg, Mikael; Öberg, Johnny; Tiensyrjä, Kari; Hemani, Ahmed

doi:10.1109/isvlsi.2002.1016885

Cited by 854 publications

(451 citation statements)

References 9 publications

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“…A homogenous NoC is one where the cores and routers are all the same, while a heterogeneous NoC selects individual cores from an IP library and may have its communication architecture customized to suit the needs of an application. Since NoC designs must be flexible enough to cover a certain range of applications, most of the state-of-the-art NoC designs use a mesh or torus topology because of its performance benefits and high degree of scalability for two-dimensional systems, yet it may not achieve the best performance for a single application [15,16]. In addition, the network layer also needs to deal with the routing data between processing elements.…”

Section: Network Layermentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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Section: Network Layermentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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“…In [3], Dally and Towels, use the on-chip network instead of ad hoc global wiring to interconnect the entire IP module on a chip. In [4] Kumar and Jantsch, implement a 2D mesh NoC architecture that consists of a mesh of IP cores with an associated router for each core. In order to optimize the results of the mapping problem, various people try to enhance the results considering different performance elements.…”

Section: Related Workmentioning

confidence: 99%

Evaluating the performance of one-dimensional chaotic maps in the network-on-chip mapping problem

Fard

Khademzade

Moein-darbari

2009

IEICE Electron. Express

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Abstract:Mapping is one of the most critical issues in designing a NoC-based system. A good mapping of an application to a NoC will lead to more traffic among resources, which are physically close on the chip. In this paper, we introduce several one-dimensional chaotic maps for solving the NoC mapping problem. In addition we compare the solution qualities in accordance with different criteria mainly communication cost and convergence time. The results confirm an increase, due to chaotic sequences, in the value of some performance indexes. Keywords: network-on-chip, mapping, chaotic maps Classification: Integrated circuits References

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“…In this context, the Network-on-Chip (NoC) paradigm was proposed to increase the performance of CMP systems by providing scalable and efficient inter-core communication through wireline routed interconnections [1]. This approach arose as opposed to the traditional bus-based architectures, which scale poorly in terms of delay and energy efficiency due to its time division multiplexing nature when the number of cores is increased.…”

Section: Introductionmentioning

confidence: 99%

Pulse interspersing in static multipath chip environments for Impulse Radio communications

Mestres

Abadal

Llátser

et al. 2016

Nano Communication Networks

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Communications are becoming the bottleneck in the performance of Chip Multiprocessor (CMP). To address this issue, the use of wireless communications within a chip has been proposed, since they offer a low latency among nodes and high reconfigurability. The chip scenario has the particularity that is static, and the multipath can be known a priori. Within this context, we propose in this paper a simple yet very efficient modulation technique, based on Impulse Radio -On-Off-Keying (IR-OOK), which significantly optimizes the performance in Wireless Network-on-Chip (WNoC) as well as off-chip scenarios. This technique is based on interspersing information pulses among the reflected pulses in order to reduce the time between pulses, thus increasing the data rate. We prove that the final data rate can be considerably increased without increasing the hardware complexity of the transceiver.

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A network on chip architecture and design methodology

Cited by 854 publications

References 9 publications

Networks on Chips: Structure and Design Methodologies

Networks on Chips: Structure and Design Methodologies

Evaluating the performance of one-dimensional chaotic maps in the network-on-chip mapping problem

Pulse interspersing in static multipath chip environments for Impulse Radio communications

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