A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories

Takeuchi, Ken; Satoh, S.; Tanaka, Tomoharu; Imamiya, K.; Sakui, Koji

doi:10.1109/vlsic.1998.688097

Cited by 15 publications

(13 citation statements)

References 2 publications

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“…Read disturb is a well-known phenomenon in NAND flash memory, where reading data from a flash cell can cause the threshold voltages of other (unread) cells in the same block to shift to a higher value [2,11,14,15,24,33]. While a single threshold voltage shift is small, such shifts can accumulate over time, eventually becoming large enough to alter the state of some cells and hence generate read disturb errors.…”

Section: Read Disturbmentioning

confidence: 99%

“…However, as its capacity increases, flash memory suffers from different types of circuitlevel noise, which greatly impact its reliability. These include program/erase cycling noise [2,3], cell-to-cell program interference noise [2,5,8], retention noise [2,4,6,7,23,24], and read disturb noise [11,14,24,33]. Among all of these types of noise, read disturb noise has largely been understudied in the past for MLC NAND flash, with no open-literature work available today that characterizes and analyzes the read disturb phenomenon.…”

Section: Introductionmentioning

confidence: 99%

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Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Cai

Luo

Ghose

et al. 2015

2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks

165

183

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Abstract-NAND flash memory reliability continues to degrade as the memory is scaled down and more bits are programmed per cell. A key contributor to this reduced reliability is read disturb, where a read to one row of cells impacts the threshold voltages of unread flash cells in different rows of the same block. Such disturbances may shift the threshold voltages of these unread cells to different logical states than originally programmed, leading to read errors that hurt endurance.For the first time in open literature, this paper experimentally characterizes read disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flash memory chips. Our findings (1) correlate the magnitude of threshold voltage shifts with read operation counts, (2) demonstrate how program/erase cycle count and retention age affect the read-disturb-induced error rate, and (3) identify that lowering pass-through voltage levels reduces the impact of read disturb and extend flash lifetime. Particularly, we find that the probability of read disturb errors increases with both higher wear-out and higher pass-through voltage levels.We leverage these findings to develop two new techniques. The first technique mitigates read disturb errors by dynamically tuning the pass-through voltage on a per-block basis. Using real workload traces, our evaluations show that this technique increases flash memory endurance by an average of 21%. The second technique recovers from previously-uncorrectable flash errors by identifying and probabilistically correcting cells susceptible to read disturb errors. Our evaluations show that this recovery technique reduces the raw bit error rate by 36%.

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Section: Read Disturbmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Cai

Luo

Ghose

et al. 2015

2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks

165

183

View full text Add to dashboard Cite

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“…In 3DVG NAND, each layer has its own BL. Thus, the application of different gate voltages ( ) for bitline (BL) clampers (BLC) in each layer enables the voltage-mode reverse-read (RR) [25] scheme to realize layer-awareverify/sensing operations within a single PV cycle. Fig.…”

Section: ) Operation Of La-pv-rmentioning

confidence: 99%

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

Hung

Chang

Yang

et al. 2015

IEEE J. Solid-State Circuits

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3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance ( ), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ( ), DNSS reduces the cross-layer -mismatch by 41%, LA-PV-R using various program-threshold-voltages ( ) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVGNAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.

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“…In the past, a large body of prior work examined the failure characteristics of flash cells in controlled environments using small numbers e.g., tens) of raw flash chips (e.g., [36,23,21,27,22,25,16,33,14,5,18,4,24,40,41,26,31,30,37,6,11,10,7,13,9,8,12,20]). This work quantified a variety of flash cell failure modes and formed the basis of the community's understanding of flash cell reliability.…”

Section: Introductionmentioning

confidence: 99%

A Large-Scale Study of Flash Memory Failures in the Field

Meza

Kumar

et al. 2015

Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems

111

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Servers use flash memory based solid state drives (SSDs) as a high-performance alternative to hard disk drives to store persistent data. Unfortunately, recent increases in flash density have also brought about decreases in chip-level reliability. In a data center environment, flash-based SSD failures can lead to downtime and, in the worst case, data loss. As a result, it is important to understand flash memory reliability characteristics over flash lifetime in a realistic production data center environment running modern applications and system software.This paper presents the first large-scale study of flash-based SSD reliability in the field. We analyze data collected across a majority of flash-based solid state drives at Facebook data centers over nearly four years and many millions of operational hours in order to understand failure properties and trends of flash-based SSDs. Our study considers a variety of SSD characteristics, including: the amount of data written to and read from flash chips; how data is mapped within the SSD address space; the amount of data copied, erased, and discarded by the flash controller; and flash board temperature and bus power.Based on our field analysis of how flash memory errors manifest when running modern workloads on modern SSDs, this paper is the first to make several major observations: (1) SSD failure rates do not increase monotonically with flash chip wear; instead they go through several distinct periods corresponding to how failures emerge and are subsequently detected, (2) the effects of read disturbance errors are not prevalent in the field, (3) sparse logical data layout across an SSD's physical address space (e.g., non-contiguous data), as measured by the amount of metadata required to track logical address translations stored in an SSD-internal DRAM buffer, can greatly affect SSD failure rate, (4) higher temperatures lead to higher failure rates, but techniques that throttle SSD operation appear to greatly reduce the negative reliability impact of higher temperatures, and (5) data written by the operating system to flash-based SSDs does not always accurately indicate the amount of wear induced on flash cells due to optimizations in the SSD controller and buffering employed in the system software. We hope that the findings of this first large-scale flash memory reliability study can inspire others to develop other publicly-available analyses and novel flash reliability solutions.

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A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories

Cited by 15 publications

References 2 publications

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

A Large-Scale Study of Flash Memory Failures in the Field

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