A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees

Mahdi, Ahmed; Kanistras, N.; Paliouras, V.

doi:10.1109/tvlsi.2020.3034046

Cited by 19 publications

(13 citation statements)

References 36 publications

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“…However, the matrix H −1 2 is dense and therefore leads to significantly high hardware cost in terms of computational complexity and memory requirements. Nevertheless, when properly exploiting the matrix structure, it is possible to achieve significant hardware cost reduction for certain codes [17][18][19].…”

Section: Partitioned Pcm Two-step Encodingmentioning

confidence: 99%

“…Such a method is computationally very expensive since, in general, the generator matrix is not sparse. Reduction of complexity can be obtained for systematic codes if the PCM is divided into two parts [17][18][19]. This way, the encoding can be performed by multiplication with two smaller matrices of which the first one is sparse, but the second one is dense.…”

Section: Introductionmentioning

confidence: 99%

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Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

2021

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Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

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Section: Partitioned Pcm Two-step Encodingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

2021

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“…In this paper, the calculation of AS T and CS T is parallelized, and the maximum parallel structures are designed according to the number of columns of A matrix and the number of rows of C matrix respectively. In the process of obtaining P 1 , in order to avoid the complexity of matrix inversion, traversing each two B submatrices of H BG1 and H BG2 , (8)(9)(10)(11) shows the four structures of the B matrix, where −1 represents the 0 matrix of Z × Z, 1 and 105 represent the Z × Z unit matrix that is right cyclic shift once and 105 times, and 0 represents the Z × Z unit matrix. Under the principle of GF(2) operations, the process of solving ( 5) can be converted to (12-15), P (α) i,j means the right barrel shift of α bits.…”

Section: Qc-ldpc High-parallel Encoding Algorithmmentioning

confidence: 99%

“…Meanwhile, a parallel matrix vector multiplication structure and storage compression are used to increase the encoding speed and significantly reduce the number of storage bits required. In [ 11 ], a fully parallel QC-LDPC encoder based on a reduced complexity XOR tree designed specifically for the IEEE 802.11n standard was proposed. In [ 12 ], a pipeline architecture for QC-LDPC encoder was proposed.…”

Section: Introductionmentioning

confidence: 99%

Low-Latency QC-LDPC Encoder Design for 5G NR

Tian

Bai

Liu

2021

Sensors

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In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.

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“…The design can realize the requirements for different encoding parameters. Reference [28] proposes a fully parallel LDPC encoder based on reduced complexity XOR trees; it is designed for the IEEE 802.11n standards. Reference [29] introduces a method to improve hardware multiplication based on constant matrices in GF (2); it tries to apply the method to the QC-LDPC encoding algorithm.…”

Section: Introductionmentioning

confidence: 99%

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Zhu¹,

Zuo-cheng²,

Li³

et al. 2021

Symmetry

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This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees

Cited by 19 publications

References 36 publications

Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Low-Latency QC-LDPC Encoder Design for 5G NR

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

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