Low-Latency QC-LDPC Encoder Design for 5G NR

Tian, Yunke; Bai, Yong; Liu, Dake

doi:10.3390/s21186266

Cited by 4 publications

(8 citation statements)

References 22 publications

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“…This study successfully maintains the error correction performance of the LDPC encoder despite implementing the fuzzy logic and DVFS approach in its logic circuit. As a result, it outperforms other approaches used in previous studies such as [13,16] and [20]. It also offers advantages over other studies that involve trade-offs, such as [18] or [19].…”

Section: Error Correction Performance Basedmentioning

confidence: 84%

“…Similarly, to meet the requirements of low latency and high throughput in 5G NR data transmission, researchers in [16] aimed to minimize encoding hardware latency and reduce base station power consumption. Their design is flexible, accommodating various code lengths and rates needed for 5G NR.…”

Section: Related Workmentioning

confidence: 99%

“…Based on this, the proposed power controller in our study demonstrates an advantage in terms of power consumption compared to previous studies that utilized different technology nodes. For instance, studies using 65-nm [13,15], 28-nm [16,18], or even 90-and 45-nm CMOS technology [17,22] may experience higher power consumption compared to our proposed approach. By leveraging the benefits of 16-nm CMOS technology, our power controller contributes to reducing overall power consumption, making it a promising solution for efficient power management in LDPC encoders.…”

Section: Comparative Analysis Cmos Technology Basedmentioning

confidence: 99%

“…International Journal of Intelligent Engineering and Systems, Vol. 16 LDPC codes offer efficient encoding, fast decoding, low latency, robust error detection and correction, and require less interleaving compared to turbo codes. They are represented by using either a parity check matrix (PCM) or a Tanner graph, both of which offer graphical depictions of the code's structure [4]: 1.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

2023

IJIES

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Low density parity check (LDPC) codes are highly regarded for their exceptional error correction capabilities, making them a preferred choice for error correction coding (ECC) in modern communication standards. These codes are implemented in specialized integrated circuits (ICs) that facilitate data transmission. However, the power requirements of complementary metal-oxide-semiconductor (CMOS) circuits, which operate across a wide frequency range, present a significant challenge for future communication systems. To address this challenge, this paper proposes a novel multi-frequency power reduction strategy for LDPC encoders. The strategy utilizes dynamic voltage and frequency scaling (DVFS), a well-established power reduction method in CMOS circuits. By combining DVFS with fuzzy logic control, the system optimizes the voltage supplied to the LDPC encoder, achieving substantial power reduction while maintaining coding efficiency, flexibility, and performance. The proposed approach dynamically adjusts the encoder's voltage levels based on real-time conditions, ensuring efficient power consumption across different frequencies. This innovative strategy aims to overcome the power challenges faced by future communication generations, which have been largely overlooked in previous research efforts. This paper aims to assess the effectiveness of a multi-frequency power reduction strategy for LDPC encoders. Through extensive analysis and evaluations, it demonstrates significant power reduction while maintaining LDPC coding efficiency. These findings contribute to the development of power-efficient LDPC encoder designs, meeting the evolving needs of communication systems. Results reveal the system's performance across different frequency ranges. In the lowfrequency range (1 MHz to 100 MHz), a remarkable 90% power reduction is achieved. In the medium-frequency range (100 MHz to 1 GHz), the reduction is 50%, while in the high-frequency range (1 GHz to 5 GHz), it reaches 20% to 14.5%. Notably, the system operates most effectively in the low and medium frequency range, providing substantial power savings. These results highlight the potential of the multi-frequency power reduction strategy for LDPC encoders in addressing power challenges across different frequencies. The significant power reduction achieved demonstrates its effectiveness and adaptability to varying frequency demands. This contributes to the development of power-efficient LDPC encoder designs, optimizing performance and energy consumption in various communication systems.

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Section: Error Correction Performance Basedmentioning

confidence: 84%

Section: Related Workmentioning

confidence: 99%

Section: Comparative Analysis Cmos Technology Basedmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

2023

IJIES

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“…In addition, the authors Nandalal and Anand Kumar [29] presented an efficient compact encoding process with the pipelining design of an LDPC Encoder with two-stage, three-stage, and Maximal Rate Pipelining (MRP) structures. While the author's Tian et al [30] investigated the parallel design and implementation of the 5G QC-LDPC encoder. Furthermore, the study presented by Petrović et al [31] proposes a novel partially parallel architecture that can provide high Hardware Usage Efficiency (HUE) while achieving LDPC encoder flexibility and support for all 5G NR codes.…”

Section: Related Workmentioning

confidence: 99%

Low Power Low-Density Parity Check Encoder Using Dynamic Voltage and Frequency Scaling Approach

Nazar¹,

Al-Doori²,

Alani³

2023

MMEP

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Low-Density Parity Check (LDPC) codes are viewed as one of the best error correction coding (ECC) methods in terms of correction efficiency. They have been used in several modern data transmission standards, where the codecs are often built inside specialized integrated circuits (ICs). On the other hand, Complementary Metal-Oxide-Semiconductor (CMOS) circuits have evolved as a critical design characteristic that the designer must consider such as power, which has been overlooked by many researchers. For that reason, in this paper, a research work that reduces LDPC encoder power consumption is presented using a well-known power reduction method named Dynamic Voltage and Frequency Scaling (DVFS), which is one of the most powerful power reduction strategies in CMOS circuits. The proposed system includes a fuzzy logic controller with the DVFS technique to control and select the optimum level of voltage that enters the encoder to reduce its total power consumption. This combination of these two techniques showed significant power reduction and control while causing no impact on the LDPC efficiency, flexibility, and performance. Comparisons with other studies covering power reduction in LDPC codes have shown that the purposed system has the best performance over similar systems in the literature.

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Advanced channel coding schemes for B5G/6G networks: State‐of‐the‐art analysis, research challenges and future directions

Gautam,

Thakur,

Singh

2024

Int J Communication

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SummaryAs a consequence of continuing demand for additional capacity and higher quality data transmission, channel coding as a key component of a digital communication network has progressed from a classical single pair, point‐to‐point information theoretic application to a class of coding techniques with diverse parameters. The heterogeneous requirements of B5G/6G networks technology have made flexibility of code parameters the main desired feature while designing channel codes. Owing to this, channel coding techniques have evolved to support enabling applications that depend on different factors such as latency, reliability, energy efficiency and throughput. We review and discuss the application of new techniques, modifications in the design and construction of modern channel coding schemes, including block, convolutional, rateless and space‐time codes. Further, the error correction performance of mainstream channel decoders for LDPC, polar and turbo codes is compared and analysed for their attainable error rate. The aim of this study is to highlight the adaptability of the discussed coding schemes for the forthcoming cellular network landscape. This article also addresses the implementational challenges of high throughput, low latency and machine type communication scenarios. Moreover, some recent studies exploring the role of machine learning for optimisation of B5G/6G networks are classified and discussed. Concluding, research areas pertaining to the scalability of error control coding for next generation networking are addressed.

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Low-Latency QC-LDPC Encoder Design for 5G NR

Cited by 4 publications

References 22 publications

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

Low Power Low-Density Parity Check Encoder Using Dynamic Voltage and Frequency Scaling Approach

Advanced channel coding schemes for B5G/6G networks: State‐of‐the‐art analysis, research challenges and future directions

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