A multi-standard video coding accelerator based on a vector architecture

Chouliaras, V.A.; Nunez, J.L.; Rovati, F.S.; Alfonso, D.

doi:10.1109/icce.2005.1429754

Cited by 7 publications

(8 citation statements)

References 2 publications

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“…Fig. 11 shows an architecture of an adder tree for RB parallel PE [3,[5][6][7][8][9][10] whereas a full resolution parallel adder tree would consist of eight 8-bit adders in the first level, four 9-bit adders in the second level, two 10-bit adders in the third level, a 11-bit adder in the fourth level and a 16-bit accumulator.…”

Section: Parallel Architecture With Parallel Pe (Full Resolution and Rb)mentioning

confidence: 99%

“…The FSME is the most computational part of MPEG2 encoder, i.e., the dynamic instruction count (instruction count at run time [5][6][7][8][9][10]) of FSME is 60% -80% of the encoder's total dynamic instruction count [3,[5][6][7][8][9][10]. The real time computational complexity of the FSME algorithm on a reduced instruction set computer (RISC) processor for a common intermediate format (CIF) video sequence involves billions of 8-bit arithmetic calculations and memory accesses per second [3].…”

Section: Introductionmentioning

confidence: 99%

“…These fast subsampling algorithms have less computational complexity although their quality can deteriorate as well. When these algorithms run on the multiprocessor based system [5][6][7][8][9][10], their computational complexity reduces further. VLSI implementations of these fast ME algorithms can become complex due to irregular data flow.…”

Section: Introductionmentioning

confidence: 99%

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Reduced bit low power VLSI architectures for motion estimation

Agha

Khan

Malik

et al. 2013

J. of Syst. Eng. Electron.

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Low power and real time very large scale integration (VLSI) architectures of motion estimation (ME) algorithms for mobile devices and applications are presented. The power reduction is achieved by devising a novel correction recovery mechanism based on algorithms which allow the use of reduced bit sum of absolute difference (RBSAD) metric for calculating matching error and conversion to full resolution sum of absolute difference (SAD) metric whenever necessary. Parallel and pipelined architectures for high throughput of full search ME corresponding to both the full resolution SAD and the generalized RBSAD algorithm are synthesized using Xilinx Synthesis Tools (XST), where the ME designs based on reduced bit (RB) algorithms demonstrate the reduction in power consumption up to 45% and/or the reduction in area up to 38%.Keywords: motion estimation (ME), very large scale integration (VLSI), reduced bit sum of absolute difference (RBSAD).

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Section: Parallel Architecture With Parallel Pe (Full Resolution and Rb)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reduced bit low power VLSI architectures for motion estimation

Agha

Khan

Malik

et al. 2013

J. of Syst. Eng. Electron.

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“…In our previous work [5], we quantified extensively the DLP for a number of video coding standards, including the open-source, integer-based MPEG-4 (XviD) implementation [6]. We take this work further by fully threading the encoder and presenting the combined DLP and TLP performance improvements obtained from a parallel-RAM (PRAM) model.…”

Section: Introductionmentioning

confidence: 99%

SystemC-defined SIMD instructions for high performance SoC architectures

Chouliaras

Koutsomyti

Jacobs

et al. 2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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This work presents a SystemC-based design of custom SIMD instructions for accelerating media and telecom codes on a next-generation configurable, extensible processor. The SS_SPARC processing platform, incorporates a generic vector unit which can be extended with pipelined, SIMD computation units (datapaths) designed either with established (RTL-based) or in this case, hybrid (SystemC-RTL) methodologies. This work elaborates on a custom methodology for automatically encapsulating the data-parallel sections of the MPEG-4 XviD the G723.1 and G729A reference codes into a SystemC wrapper which is subsequently synthesized to RTL with a commercial SystemC-synthesis tool. The resulting RTL is then attached to the exposed vector unit of the SS_SPARC engine. We present results from a standard-cell RTL synthesis campaign and the VLSI implementation of a high-end (8-contexts, 256 bit) and a low-end (2-context, 128 bit) configuration of the vector engine for the workloads of interest.

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“…These standards enabled major reductions in the channel bit-rates via advanced compression algorithms exploiting redundancy in the spatial (intra-frame) and temporal (inter-frame) dimensions of the input video sequence. A common characteristic of all three standards is the very high computational requirements of the encoding process [4]. For the MPEG-4 in particular, our data indicate that 400 MIPS are required to achieve 30 Frame-persecond (FPS) at QCIF resolution (176x144).…”

Section: Introductionmentioning

confidence: 96%

Configurable Multiprocessors for High-Performance MPEG-4 Video Coding

Chouliaras

Jacobs

Kwnaraswamy

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardwarebased multi-processing primitives and associated support state and implemented a parametric, busbased SoC multiprocessor as the target platform for the threaded video encoder.

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A multi-standard video coding accelerator based on a vector architecture

Cited by 7 publications

References 2 publications

Reduced bit low power VLSI architectures for motion estimation

Reduced bit low power VLSI architectures for motion estimation

SystemC-defined SIMD instructions for high performance SoC architectures

Configurable Multiprocessors for High-Performance MPEG-4 Video Coding

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