SystemC-defined SIMD instructions for high performance SoC architectures

Abstract

This work presents a SystemC-based design of custom SIMD instructions for accelerating media and telecom codes on a next-generation configurable, extensible processor. The SS_SPARC processing platform, incorporates a generic vector unit which can be extended with pipelined, SIMD computation units (datapaths) designed either with established (RTL-based) or in this case, hybrid (SystemC-RTL) methodologies. This work elaborates on a custom methodology for automatically encapsulating the data-parallel sections of the MPEG-4 XviD the G723.1 and G729A reference codes into a SystemC wrapper which is subsequently synthesized to RTL with a commercial SystemC-synthesis tool. The resulting RTL is then attached to the exposed vector unit of the SS_SPARC engine. We present results from a standard-cell RTL synthesis campaign and the VLSI implementation of a high-end (8-contexts, 256 bit) and a low-end (2-context, 128 bit) configuration of the vector engine for the workloads of interest.

A configurable length, Fused Multiply-Add floating point unit for a VLIW processor

“…The FMA unit, presented in this paper, has been integrated in the LE1 Multi-Cluster VLIW processor [10], [11], [12]. The LE1 is a configurable, extensible, multi-cluster VLIW architected in a way to allow for the customization of the architecture (Register files, size, number, SIMD capability) and microarchitecture (custom ISA support, streaming memories etc).…”

Embedded UML design flow to the configurable LE1 MultiCore VLIW processor

“…The base Instruction Set Architecture (ISA) for the LE1 is an amalgam of the partially-predicated Multiflow TRACE architecture [17], fully-predicated EPIC architectures [18], augmented with substantial Single Instruction Single Data (SIMD) support [19]. This model (ISA, state) can be extended with additional registers and single/multi-input, multi-output custom extensions.…”

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

“…LE1 CONFIGURABILITY LE1 has been architected to be highly parameterizable in both the programmer model (architectural parameterization) as well as its internal organization (microarchitecture customization). The base ISA is an amalgam of the partiallypredicated Multiflow TRACE architecture [11], fullypredicated EPIC architectures [12], augmented with substantial SIMD support [13]. This model (ISA, state) can be extended with additional registers and single/multi-input, multi-output custom extensions.…”