LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

Abstract

We discuss LE1, a parameterized VLIW Chip Multiprocessor (CMP) adhering to the shared memory programmers model. LE1's novelty lies in its ability to perform dynamic thread-spawning through hardware support for PThread-like primitives in addition to its substantial architectural and microarchitectural parameterization. Dynamic (hardware) thread creation is very fast and removes the need for an executive/OS, presenting to the application programmer a 'bare-metal' multiprocessor, capable of exploiting all forms of parallelism. The core LE1 CPU is a configurable, 8-stage pipeline VLIW engine with a proprietary Instruction Set Architecture (ISA) supporting both partial and full predication and pipelined, multi-input, multi-output (MIMO) instruction extensions. The LE1 CMP is parameterizable as to the number of processors, their issue capability, internal microarchitectural features, functional unit mix and latency and the local memory system architecture.Preliminary results indicate near-linear performance improvement when executing a threaded version of the Mandelbrot calculation on 2-way and 4-way processor configurations with a 256 KB, 4-way banked tightly-coupled memory system. Similar trends are seen when executing a threaded matrix multiplication benchmark. We present these findings along with VLSI implementations of 4-way, dual-issue and 3-way, quad issue multiprocessor configurations.

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

“…2 and consists of a standard host processor (Leon3 for standard-cell technologies and the Xilinx Microblaze for FPGA targets) and a number of default peripherals. A key component of the flow is the multi-core VLIW engine [16,17] (Figs. 2b and 2c) which forms the first-level accelerator.…”

Embedded UML design flow to the configurable LE1 MultiCore VLIW processor

“…The LE1 Tool Collection [12] [13] consists of several tools and scripts needed for the compilation of C code onto the highly parallel LE1 VLIW multi-core processor. The LE1 system tool chain consists of a research retargetable compiler [14] with a custom LE1 back-end target, a collection of compilation scripts, and the cycle-accurate simulation infrastructure for the LE1.…”

“…In the ENOSYS framework, the LE1 soft core processor [12] [13] is responsible for servicing the parts of the UML diagram assigned with software stereotypes. The architecture of the LE1 has been designed in such a way to be highly parameterisable in both the programmer model (architectural parametrisation) it presents to the programmer as well as its internal organisation (micro-architecture customisation).…”

An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor

“…This research is motivated by the ever-increasing adoption of the Single Instruction Multiple Thread (SIMT) processing paradigm (via OpenCL) for advanced FPGA design and this paper presents an automated compilation framework that enables parallel computation, through the execution of OpenCL kernels 2 on a configurable VLIW Chip Multiprocessor (CMP) [7][8]. The LE1 architecture (Section III-A) is both configurable and extensible and is designed for embedded DSP applications on FPGA and standard-cell silicon.…”