Configurable Multiprocessors for High-Performance MPEG-4 Video Coding

Abstract

We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardwarebased multi-processing primitives and associated support state and implemented a parametric, busbased SoC multiprocessor as the target platform for the threaded video encoder.