A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

Kim, Suhwan; Kosonocky, Stephen; Knebel, D.R.; Stawiasz, K.; Papaefthymiou, Marios C.

doi:10.1109/tcsii.2007.894428

Cited by 66 publications

(49 citation statements)

References 18 publications

(14 reference statements)

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“…While PU6 is near the center of the chip and has lower peak noise of around 160 mV. Kim et al reported similar observations in [38] that the power gating induced P/G noise for a small circuit of two linear-feedback shift registers and a 32-bit carry look-ahead adder fabricated with 130 nm technology is already about 9 percent of the supply voltage and becomes a reliability threat in low power circuit design. Different impact ranges can be observed in Fig.…”

Section: The Physical Model Of Power Gating-induced P/g Noisymentioning

confidence: 68%

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuitlevel MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.

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Section: The Physical Model Of Power Gating-induced P/g Noisymentioning

confidence: 68%

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Liu

Wang

et al. 2013

IEEE Trans. Parallel Distrib. Syst.

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“…Because of the self-inductance of the off-chip bonding wires and the parasitic inductance inherent to the on-chip power rails, these surges result in voltage fluctuations in the power rails. If the magnitude of the voltage surge or droop is greater than the noise margin of a circuit, that circuit may erroneously latch to the wrong value or switch at the wrong time [7][8]10]. Inductive noise, also known as simultaneous switching noise, is a phenomenon that has been traditionally associated with input/output buffers and internal circuitry.…”

Section: Ground Bounce Noise Reductionmentioning

confidence: 99%

“…Without a clear understanding of the technique, however, the negative effects of power gating, such as, inductive noise and the range of device options, make it difficult to realize the potential benefits. Ground bounce is induced by an instantaneous power mode transition of a sleep transistor in a power gating structure [7][8].…”

Section: Introductionmentioning

confidence: 99%

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

Lee¹,

Lee²,

Woo

et al. 2008

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudorandom manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

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“…To preserve the data in the circuit block during idle periods, an intermediate data retention mode is required. Many power gating techniques [6][7][8][9] have been proposed for leakage reduction and data retention. In all these techniques, the charge gets stored at the gate of the sleep transistor during active mode.…”

Section: Introductionmentioning

confidence: 99%

Low leakage power gating technique for subnanometer CMOS circuits

Kavitha¹,

Thangavel²

2016

Turk J Elec Eng & Comp Sci

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Abstract:Static power has become the most important factor in the fabrication of integrated circuits. Power gating techniques minimize leakage currents and help to develop ultra-low-power and high-performance digital circuits. In this paper, a power gating approach is proposed to minimize leakage for subnanometer technologies. Simulation results reveal that the proposed technique reduces maximum of 96% leakage power, 33% dynamic power, 49% drowsy power, and 16% energy as compared to conventional techniques. The proposed technique offers good leakage reduction, even under variation of different operating parameters.

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A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

Cited by 66 publications

References 18 publications

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

Low leakage power gating technique for subnanometer CMOS circuits

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