A multi-Gbps unrolled hardware list decoder for a systematic polar code

Giard, Pascal; Balatsoukas‐Stimming, Alexios; Müller, Thomas Christoph; Burg, Andreas; Thibeault, Claude; Gross, Warren J.

doi:10.1109/acssc.2016.7869561

Cited by 9 publications

(12 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On architectural level, unrolling and pipelining of the PFT traversal for the SCL algorithm can be performed in the same way as for the SC algorithm [12]. The high throughput gained by unrolling and pipelining comes at the cost of flexibility, since resulting decoders are specialized for a specific code and rate.…”

Section: B Scl Decodingmentioning

confidence: 99%

“…It is impractical to consider all L • 2 Nv possible codewords, thus different approaches were presented in literature. The architecture of [12] implements the algorithm of [9] where an approximation is introduced to reduce the number of candidate paths. They split the decoding path only for the two least reliable bits in the Rate-1 node.…”

Section: A Rate-1 Nodementioning

confidence: 99%

“…At the architectural level, an unrolling of the PFT traversal and corresponding pipelining mitigates the sequential data dependencies and, thus, enables very high throughput. The principle of unrolling, applied to LDPC in decoders [10], was later adopted for Polar code decoding with SC [11] and SCL [12]. 644 Gbit/s coded throughput is reported for SC based decoder in a 28 nm technology in [13].…”

Section: Introductionmentioning

confidence: 99%

“…After placement and routing, a much lower throughput is expected. As of today, only one publication of an unrolled SCL decoder exists which achieves 12 Gbit/s coded throughput in a 28 nm technology [12].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 506Gbit/s Polar Successive Cancellation List Decoder with CRC

Kestel

Johannsen

Griebel

et al. 2020

2020 IEEE 31st Annual International Symposium on Personal, Indoor and Mobile Radio Communications

View full text Add to dashboard Cite

Polar codes have recently attracted significant attention due to their excellent error-correction capabilities. However, efficient decoding of Polar codes for high throughput is very challenging. Beyond 5G, data rates towards 1 Tbit/s are expected. Low complexity decoding algorithms like Successive Cancellation (SC) decoding enable such high throughput but suffer on errorcorrection performance. Polar Successive Cancellation List (SCL) decoders, with and without Cyclic Redundancy Check (CRC), exhibit a much better error-correction but imply higher implementation cost. In this paper we in-depth investigate and quantify various trade-offs of these decoding algorithms with respect to error-correction capability and implementation costs in terms of area, throughput and energy efficiency in a 28 nm CMOS FD-SOI technology. We present a framework that automatically generates decoder architectures for throughputs beyond 100 Gbit/s. This framework includes various architectural optimizations for SCL decoders that go beyond State-of-the-Art. We demonstrate a 506 Gbit/s SCL decoder with CRC that was generated by this framework.

show abstract

Section: B Scl Decodingmentioning

confidence: 99%

Section: A Rate-1 Nodementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 506Gbit/s Polar Successive Cancellation List Decoder with CRC

Kestel

Johannsen

Griebel

et al. 2020

2020 IEEE 31st Annual International Symposium on Personal, Indoor and Mobile Radio Communications

View full text Add to dashboard Cite

show abstract

“…Various hardware implementations for Polar Code decoders have been proposed in recent years. They cover pipelined high-throughput architectures (Giard et al, 2017), flexible (Dizdar and Arıkan, 2016), and iterative decoder implementations (Park et al, 2014) to name but a few of them. These decoders are generally optimized only for one specific target, e.g., throughput, area or code rate flexibility, and especially for only one specific decoding algorithm.…”

Section: Introductionmentioning

confidence: 99%

Polar Code decoder exploration framework

2018

View full text Add to dashboard Cite

Abstract. The increasing demand for fast wireless communications requires sophisticated baseband signal processing. One of the computational intense tasks here is advanced Forward Error Correction (FEC), especially the decoding. Finding efficient hardware implementations for sophisticated FEC decoding algorithms that fulfill throughput demands under strict implementation constraints is an active research topic due to increasing throughput, low latency, and high energy efficiency requirements. This paper focuses on the interesting class of Polar Codes that are currently a hot topic. We present a modular framework to automatically generate and evaluate a wide range of Polar Code decoders, with emphasis on design space exploration for efficient hardware architectures. To demonstrate the efficiency of our framework a very high throughput Soft Cancellation (SCAN) Polar Code decoder is shown that was automatically generated. This decoder is, to the best of our knowledge, the fastest SCAN Polar Code decoder published so far.

show abstract

The implementation of Shannon-limited polar codes-based information reconciliation for quantum key distribution

Guo¹,

Tang²,

Lai³

et al. 2023

Quantum Sci. Technol.

View full text Add to dashboard Cite

Quantum key distribution (QKD) gives a way to generate unconditionally secure keys for two remote users, Alice and Bob. Information reconciliation (IR), which can correct the errors caused by the imperfection of the QKD systems, is a critical component in QKD. Due to the high-security requirements and large volumes of data processing, the robustness and efficiency are two main factors that must be considered for the implementation of IR. The polar codes-based IR has potential advantages, such as, capacity to reach Shannon-limit, high IR efficiency and low computational complexity. Although CPU-based IR is always implemented in most of the previous works, it is not the optimal implementation in terms of performance and power dissipation. To the best of our knowledge, there is still no work to build a special purpose hardware module for polar codes-based IR. In this paper, a dedicated design of hardware accelerator is first proposed for polar codes-based IR, in which the block checked successive cancellation list (BC-SCL) algorithm is used to verify the consistency of the sifted keys, and the overall failure probability of IR is significantly reduced. The proposed design is constructed into a partially-unrolled parallel architecture to accelerate the core decoder as well as balance the resource consumption. Furthermore, the hardware implementation is completed based on the Xilinx Zynq UltraScale+ XCZU5EV platform and achieves an IR throughput of 15 Mbps with a block length of 2^(12), while less than 20% of the amount of on-chip resource is used in other previous designs of SCL decoder. The proposed design can provide a real-time, low-cost solution for IR in QKD systems, and enhance the performance of QKD.

show abstract

A multi-Gbps unrolled hardware list decoder for a systematic polar code

Cited by 9 publications

References 20 publications

A 506Gbit/s Polar Successive Cancellation List Decoder with CRC

A 506Gbit/s Polar Successive Cancellation List Decoder with CRC

Polar Code decoder exploration framework

The implementation of Shannon-limited polar codes-based information reconciliation for quantum key distribution

Contact Info

Product

Resources

About