A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

Wang, Junliang; Wang, Zhigong; Xu, Jun; Tian, Mi; Lei, Xuemei; Ma, Lianliang; Tang, Lu

doi:10.1007/s10470-014-0341-x

Cited by 2 publications

(1 citation statement)

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“…Phase-locked loop (PLL)-type frequency synthesizers are widely used to generate local frequency signals in RF transceivers. Programmable frequency dividers are indispensable in PLL-type frequency synthesizers [1][2][3]. Important specifications, such as a wide operation frequency range, low phase noise, and low power consumption are significant to programmable frequency dividers [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

et al. 2021

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A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

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