2021
DOI: 10.3390/electronics10202494
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A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

Abstract: A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency … Show more

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Cited by 2 publications
(2 citation statements)
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“…Lin et al propose a variation [24] based on (one/two) divider cells achieving a full range, such that 1 ≤ N ≤ 2 w . Yet another widely used architecture, known as the pulse swallow frequency divider [16,[25][26][27][28][29][30], is based on a combination of a dual-modulus prescaler (divides by P or P + 1) [31,32], a programmable counter (divide-by-N), and a swallow counter (divide-by-S). The achieved output frequency can be specified as f out = f in /(NP + S).…”
Section: Previous Programmable Countersmentioning
confidence: 99%
“…Lin et al propose a variation [24] based on (one/two) divider cells achieving a full range, such that 1 ≤ N ≤ 2 w . Yet another widely used architecture, known as the pulse swallow frequency divider [16,[25][26][27][28][29][30], is based on a combination of a dual-modulus prescaler (divides by P or P + 1) [31,32], a programmable counter (divide-by-N), and a swallow counter (divide-by-S). The achieved output frequency can be specified as f out = f in /(NP + S).…”
Section: Previous Programmable Countersmentioning
confidence: 99%
“…In various systems, including satellite communication, RF circuits, and optical communication, a frequency divider plays a vital role. It finds applications in a wide range of scenarios, including phase-locked loops (PLLs) [1,2,3,4], clock and clock recovery circuits [5,6,7], as well as orthogonal signal generation [8,9,10].With the continuous increase in data rates and system performance, there is an increasing need to develop frequency dividers capable of operating in higher frequency. So far, numerous dividers based on different topologies and processes have been reported.…”
Section: Introductionmentioning
confidence: 99%