A novel four‐stage fully differential ring voltage controlled oscillator (VCO) is presented and implemented in 0.18 μm CMOS technology. The fully differential delay cell is chosen over the pseudo‐differential one to avoid the cross‐coupling pair, increase the oscillation frequency and improve common‐noise suppression. The inductive shunt peaking technique with active inductors instead of its passive counterpart is used to expand the bandwidth of the delay cell and then increase the oscillation frequency of the VCO without the expense of excessive area. The current bleeding transistor pair is connected in shunt with the tuning transistor pair in order to make sure the VCO oscillate over the entire tuning voltage with proper phase noise. Measurement results show that, from a single voltage supply of 1.8 V and an occupied area of 475 μm × 275 μm, the proposed VCO achieves an oscillation frequency range from 3.25 to 4.2 GHz with the optimum phase noise of −92.28 dBc/Hz at 1 MHz and an optimum FOM of −154.80 dBc/Hz.
This paper presents a 37 Gb/s phase lockedloop (PLL)-type clock recovery (CR) circuit designed and fabricated in 0.2-lm GaAs PHEMT process. The resonator of the modified LC-VCO is based on a compact circuit topology with high Q-value and better isolation. The active amplifier of the VCO is optimized with a combination of several circuit techniques to reduce phase noise and increase the operation speed. Resonant filters containing high-quality CPWs are employed in the signal preprocessor to accommodate the 37 Gb/s data rate. The measured figure of merit of the modified VCO is about -196 dBc/Hz at 37-GHz when the PLL is locked. The experimental results also demonstrate that the recovered clock signal of the CR circuit has a phase noise of -81.66 dBc/Hz at 50 kHz off the center frequency.
A new compact model has been introduced to model on-chip spiral transformers. Unlike conventional models, which are often a compound of two spiral inductor models (i.e., the combination of two coupled … or 2-… sub-circuits), our new model only uses 12 elements to model the whole structure in the form of T topology. The new model is based on the physical meaning, and the process of model derivation is also presented. In addition, a simple parameter extraction procedure is proposed to get the elements' values without any fitting and optimization. In this procedure, a new method has been developed for the parameter extraction of the ladder circuit, which is commonly used to represent the skin effect. In order to verify the model's validity and accuracy, we have compared the simulated and measured self-inductance, quality factor, coupling coefficient and insertion loss, and an excellent agreement has been found over a broad frequency range up to the resonant frequency.
A W‐band injection‐locked frequency divider (ILFD) with modified transformer coupling resonant is demonstrated and implemented in a 40‐nm CMOS technology. The locking range and operation frequency of the ILFD is improved without increasing chip area or circuit complexity. The measured locking range of the ILFD covers from 86 to 104 GHz. The measured phase noise of the modified W‐band ILFD is −114.89 dBc/Hz at 1 MHz. The ILFD also attains a figure of merit normalized (FoM) of 243.1.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.