A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms

Bianchi, Valentina; Munari, Ilaria De

doi:10.1016/j.micpro.2020.103106

Cited by 25 publications

(2 citation statements)

References 13 publications

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“…These power controls generally lack precision and do not work in real time; to overcome these limitations, different solutions relying on FPGA (Field Programmable Gate Array)-implemented algorithms can be exploited [5]. In the last few years, the application of FPGA devices has increased exponentially in a wide variety of fields, such as: digital signal processing [6][7][8][9][10], data processing [11,12], bioinformatics [13,14] and power electronics [15][16][17]. Among the applications based on FPGAs that recently have been applied to the smart grid field, MPC (Model Predictive Control) has particular importance [18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices

Saccenti

Bianchi

Munari

2021

ASI

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In a multiple parallel-connected inverters system, limiting the circulating current phenomenon is mandatory since it may influence efficiency and reliability. In this paper, a new control method aimed at this purpose and conceived to be implemented on a Field Programmable Gate Array (FPGA) device is presented. Each of the inverters, connected in parallel, is conceived to be equipped with an FPGA that controls the Pulse-Width Modulation (PWM) waveform without intercommunication with the others. The hardware implemented is the same for every inverter; therefore, the addition of a new module does not require redesign, enhancing system modularity. The system has been simulated in a Simulink environment. To study its behavior and to improve the control method, simulations with two parallel-connected inverters have been firstly conducted, then additional simulations have been performed with increasing complexity to demonstrate the quality of the algorithm. The results prove the ability of the method proposed to limit the circulating currents to negligible values.

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Section: Introductionmentioning

confidence: 99%

Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices

Saccenti

Bianchi

Munari

2021

ASI

Self Cite

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“…As a result, numerous methods and hardware realization have been proposed to enhance modular multiplication. Configurable based designs are discussed completely modular and are conceived in [6]. The study of digit serial modular multiplication is distinguished in [7].…”

Section: Introductionmentioning

confidence: 99%

FPGA realization of low power multi-layer perceptron full adder to minimize EDP of modular multiplier

Pakkiraiah¹,

Satyanarayana²

2021

IJEEA

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Public key cryptography has been one of the important areas of research for design engineers due to the significance of security in data transmissions. Modular multiplication is part of the most effective cryptographic algorithms. Reduced switching activity factor and cell count are needed in the design of low-power and energy-efficient portable processors for image and digital signal processing, as well as cryptography applications. For public key cryptographic implementations such as digital signature algorithms, RSA algorithms, and ECC algorithms, crypto-primitives are needed to perform modular multiplication on large integers over finite fields. The research for modular multiplier implementations that use less power and have few cells continues, especially for crypto processors, security units, and CPU portable designs. The modular multiplier receives mainly binary input and produces a binary modular product output. This paper introduces a new Multi-Layer Perceptron (MLP) based modular multiplier architecture that uses less dynamic power dissipation. When compared to Proposed Full Adder [1] based Modular multiplier (MM), experimental results shows that the MLP based MM approach can achieve significant reductions in dynamic power dissipation and EDP. In this work, the Xilinx Vivado design suite for the Zynq-7000 family of devices is used to synthesize MLP Full Adder (MLPFA), PFA based MM (PMM) and MLP based MM (MLPMM). Based on implementation results, the MLPMM circuit consumes less dynamic power dissipation than the PFA method. In addition, the implementation results are subjected to a formula-based evaluation in order to determine the design's EDP. When compared to a PFA based modular multiplier, the MLPMM architecture can improve dynamic power dissipation and EDP approximately by 18%.

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HDL Code Generation from SIMULINK Environment for Li-Ion Cells State of Charge and Parameter Estimation

Stighezza

Bianchi

Munari

2021

Lecture Notes in Electrical Engineering

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A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms

Cited by 25 publications

References 13 publications

Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices

Study of a Synchronization System for Distributed Inverters Conceived for FPGA Devices

FPGA realization of low power multi-layer perceptron full adder to minimize EDP of modular multiplier

HDL Code Generation from SIMULINK Environment for Li-Ion Cells State of Charge and Parameter Estimation

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