FPGA realization of low power multi-layer perceptron full adder to minimize EDP of modular multiplier

Abstract

Public key cryptography has been one of the important areas of research for design engineers due to the significance of security in data transmissions. Modular multiplication is part of the most effective cryptographic algorithms. Reduced switching activity factor and cell count are needed in the design of low-power and energy-efficient portable processors for image and digital signal processing, as well as cryptography applications. For public key cryptographic implementations such as digital signature algorithms, RSA algorithms, and ECC algorithms, crypto-primitives are needed to perform modular multiplication on large integers over finite fields. The research for modular multiplier implementations that use less power and have few cells continues, especially for crypto processors, security units, and CPU portable designs. The modular multiplier receives mainly binary input and produces a binary modular product output. This paper introduces a new Multi-Layer Perceptron (MLP) based modular multiplier architecture that uses less dynamic power dissipation. When compared to Proposed Full Adder [1] based Modular multiplier (MM), experimental results shows that the MLP based MM approach can achieve significant reductions in dynamic power dissipation and EDP. In this work, the Xilinx Vivado design suite for the Zynq-7000 family of devices is used to synthesize MLP Full Adder (MLPFA), PFA based MM (PMM) and MLP based MM (MLPMM). Based on implementation results, the MLPMM circuit consumes less dynamic power dissipation than the PFA method. In addition, the implementation results are subjected to a formula-based evaluation in order to determine the design's EDP. When compared to a PFA based modular multiplier, the MLPMM architecture can improve dynamic power dissipation and EDP approximately by 18%.