A modified clock scheme for a low power BIST test pattern generator

Girard, Patrick; Guiller, L.; Landrault, C.; Pravossoudovitch, S.; Wunderlich, Hans-Joachim

doi:10.1109/vts.2001.923454

Cited by 95 publications

(73 citation statements)

References 13 publications

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“…All benchmarks have higher power reductions with TPGs in [5] than with the proposed TPGs. It also can be seen that the proposed TPG achieves lower stuck-at fault coverage for C6288 and higher stuck-at fault coverage for C7552 compared with [4]. For both benchmarks, the proposed TPGs reduce average power more effectively than TPGs in [4].…”

Section: Principle Of the Proposed Tpgmentioning

confidence: 86%

“…It also can be seen that the proposed TPG achieves lower stuck-at fault coverage for C6288 and higher stuck-at fault coverage for C7552 compared with [4]. For both benchmarks, the proposed TPGs reduce average power more effectively than TPGs in [4]. As for the test area overhead, both TPGs in [4,5] need additional combinational gates and the normal LFSR or one dimensional cellular automata to implement.…”

Section: Principle Of the Proposed Tpgmentioning

confidence: 94%

“…Looking back to study the structure of DS-LFSR in [3], we can find that it imposes larger area overhead than the proposed TPG. Table III compares the stuck-at fault coverage and the average power reduction of the proposed TPG and TPGs in [4,5]. In this table, subcolumns ΔP avg mean the average power reductions of the CUTs with these TPGs against the normal LFSR.…”

Section: Principle Of the Proposed Tpgmentioning

confidence: 99%

“…For both benchmarks, the proposed TPGs reduce average power more effectively than TPGs in [4]. As for the test area overhead, both TPGs in [4,5] need additional combinational gates and the normal LFSR or one dimensional cellular automata to implement. They impose more test area overhead than the proposed TPGs do.…”

Section: Principle Of the Proposed Tpgmentioning

confidence: 99%

“…One of these approaches is called dual speed LFSRs (DS-LFSR), which can reduce transition densities of the CUT [3]. Other approaches include the modified clock scheme [4], weighted LFSR [5], and cellular automaton (CA). Random access scan (RAS) [6] and single input change (SIC) sequences [7] offer promising solutions to reduce test power.…”

Section: Introductionmentioning

confidence: 99%

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A low cost test pattern generator for test-per-clock BIST scheme

Lei

Wang

Liu

et al. 2010

IEICE Electron. Express

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Abstract:Test power and test overhead are crucial to VLSI and SOC testing. This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can achieve high fault coverage and effectively reduce test power. Keywords: Built-in self-test, test-per-clock, test pattern generation, single input change, low power Classification: Integrated circuits References[1] R. S. Katti, X. Ruan, and H. Khattri, "Multiple-output low-power linear feedback shift register design," IEEE Trans.

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Section: Principle Of the Proposed Tpgmentioning

confidence: 86%