Models for Power-Aware Testing

Girard, Patrick; Wunderlich, Hans-Joachim

doi:10.1007/978-90-481-3282-9_7

Cited by 1 publication

(1 citation statement)

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“…Compared to the functional operation of a design, scan testing generates much higher switching activity in a module [4] and great effort is put into optimizing test patterns [5], scan clock schemes [6], and test schedules [7][8][9][10] to keep test power within affordable limits [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Scan Test Power Simulation on GPGPUs

Holst

Schneider

Wunderlich

2012

2012 IEEE 21st Asian Test Symposium

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The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands.We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models.

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