A Designer’s Guide to Built-In Self-Test

Stroud, Charles E.

doi:10.1007/b117480

Cited by 77 publications

(7 citation statements)

References 8 publications

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“…The issue disclosed in Example 1 can be formulated in a more general way; i.e., a low phase shift between test bit sequences appearing at neighboring outputs of a pseudo-random TPG leads to a strong correlation between test vectors supplied to scan paths fed from these outputs. It is why these vectors may no longer be considered as pseudo-random ones, which adversely affects the fault coverage in digital CUTs with the STUMPS-type LBIST architecture [3] (pp. 177-181), [12,[34][35][36][37].…”

Section: Examplementioning

confidence: 99%

“…A very popular LBIST architecture operated in the test-per-scan mode is STUMPS (Self-Test Using MISR/Parallel Shift register sequence generator) [1], [2] (pp. 288-290), [3] (pp. 176-177), [4] (pp.…”

Section: Introductionmentioning

confidence: 99%

“…The PRPG module is intended to supply pseudo-random sequences of bits simultaneously to all scan paths of a circuit to be tested, and these sequences are then delivered as parallel test vectors to inputs of combinational logic blocks of such a Circuit Under Test (CUT). A PRPG module is usually designed as a shift register with linear feedback (Linear Feedback Shift Register-LFSR) [3] (pp. [65][66][67][68][69][70][71][176][177], although Cellular Automata (CA) can also be used for these purposes [3] (pp.…”

Section: Introductionmentioning

confidence: 99%

“…A PRPG module is usually designed as a shift register with linear feedback (Linear Feedback Shift Register-LFSR) [3] (pp. [65][66][67][68][69][70][71][176][177], although Cellular Automata (CA) can also be used for these purposes [3] (pp. 72-75), [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

“…The final content of the MISR is referred to as the signature, which provides information on whether the CUT is faulty or not. The substantial advantage of LBIST structures with the STUMPS architecture consists of the fact that such solutions offer much shorter testing times as compared to conventional built-in self-test solutions operated in the test-per-scan mode since pseudo-random sequences of bits are supplied simultaneously to a plurality of scan paths [3] (pp. 176-177).…”

Section: Introductionmentioning

confidence: 99%

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A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Garbolino

2021

Applied Sciences

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Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT‑LFSR‑TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

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