A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores

Aamir, Syed Ahmed; Müller, Paul; Kiene, Gerd; Kriener, Laura; Stradmann, Yannik; Grübl, Andreas; Schemmel, Johannes; Meier, K.

doi:10.1109/tbcas.2018.2848203

Cited by 43 publications

(29 citation statements)

References 58 publications

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“…[12][13][14][15][16][17][18][19][20] However, there are limited studies that show hardware implementation of adaptive/ dynamically adaptive neuron functions. Mixed signal silicon implementation of adaptive neuron models exploiting membrane dynamics like Mihalas-Niebur model 9 and adaptive exponential decay model (AdeX) 8 have been shown in 21,22 . Wang et al 23 have recently simulated a RRAM device to realize an adaptive neuron, in which the adaptation behavior is achieved by increasing the neuron membrane resistance at each spike event.…”

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confidence: 99%

An adaptive threshold neuron for recurrent spiking neural networks with nanodevice hardware implementation

Shaban

Bezugam

2021

Nat Commun

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We propose a Double EXponential Adaptive Threshold (DEXAT) neuron model that improves the performance of neuromorphic Recurrent Spiking Neural Networks (RSNNs) by providing faster convergence, higher accuracy and a flexible long short-term memory. We present a hardware efficient methodology to realize the DEXAT neurons using tightly coupled circuit-device interactions and experimentally demonstrate the DEXAT neuron block using oxide based non-filamentary resistive switching devices. Using experimentally extracted parameters we simulate a full RSNN that achieves a classification accuracy of 96.1% on SMNIST dataset and 91% on Google Speech Commands (GSC) dataset. We also demonstrate full end-to-end real-time inference for speech recognition using real fabricated resistive memory circuit based DEXAT neurons. Finally, we investigate the impact of nanodevice variability and endurance illustrating the robustness of DEXAT based RSNNs.

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mentioning

confidence: 99%

An adaptive threshold neuron for recurrent spiking neural networks with nanodevice hardware implementation

Shaban

Bezugam

2021

Nat Commun

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“…For the BrainScaleS systems, the use of teststand has lead to large increase of in-silicon usability. It was used throughout the verification of various components of the BrainScaleS-2 ASICs, including the current neuron implementation [2,35]. As a more compact example of teststand usage, we want to present a verification strategy for the BrainScaleS-2 synapse driver circuit, focussing on the analog implementation of short-term plasticity (STP).…”

Section: Monte Carlo Calibrationmentioning

confidence: 99%

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

Grübl

Billaudelle

Cramer

et al. 2020

J Sign Process Syst

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This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

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“…3 is a neuromorphic implementation of the ∆ modulator block of Fig. 2 that is adapted from commonly used silicon neuron circuits in the literature [1,2]. It is a current-mode circuit where the filter E(s) integrates the difference between the input and feedback outputs.…”

Section: The Adexpif and σ∆ Neuron Circuitsmentioning

confidence: 99%

“…We only report area and power comparisons at a spike generation rate of 300 Hz as literature on temporal data encoding performance of spiking neurons is very scarce (see Table I). The mixed-signal neuron designs in BrainScaleS [20] and Neurogrid [3] offer the closest comparison to this work. TrueNorth [21], Loihi [22] and ODIN [23] are digital systems that use advanced processes, time-multiplexing of neurons and low supply voltages.…”

Section: Comparison To Other Neuron Implementationsmentioning

confidence: 99%

“…However, the computation of neural network models on traditional von Neumann style processors tends to consume considerable amounts of energy, making them nonviable in such powerstarved conditions. Event-based neuromorphic processing is an alternative computational approach that tries to address this problem by a combination of in-memory and asynchronous communication techniques [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

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An Ultra-Low Power Sigma-Delta Neuron Circuit

Nair

Indiveri

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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Neural processing systems typically represent data using Leaky Integrate and Fire (LIF) neuron models that generate spikes or pulse trains at a rate proportional to their input amplitudes. This mechanism requires high firing rates when encoding time-varying signals, leading to increased power consumption. Neuromorphic systems that use adaptive LIF neuron models overcome this problem by encoding signals in the relative timing of their output spikes rather than their rate. In this paper, we analyze recent adaptive LIF neuron circuit implementations and highlight the analogies and differences between them and a first-order Σ∆ feedback loop. We propose a new Σ∆ neuron circuit that addresses some of the limitations in existing implementations and present simulation results that quantify the improvements. We show that the new circuit, implemented in a 1.8V , 180nm CMOS process, offers up to 42dB Signal to Distortion Ratio (SDR) and consumes orders of magnitude lower energy. Finally, we also demonstrate how the sigma-delta interpretation enables mapping of real-valued Recurrent Neural Networks (RNNs) to the spiking framework to emphasize the envisioned application of the proposed circuit.

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A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores

Cited by 43 publications

References 58 publications

An adaptive threshold neuron for recurrent spiking neural networks with nanodevice hardware implementation

An adaptive threshold neuron for recurrent spiking neural networks with nanodevice hardware implementation

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

An Ultra-Low Power Sigma-Delta Neuron Circuit

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