Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

Abstract

This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

Brain-Inspired Spiking Neural Networks

“…PyNN officially supports BRIAN, NEST and NEURON SNN simulation tools. It is also supported on SpiNNaker [51] and BrainScaleS-2 [52] neuromorphic hardware systems. There are several more simulation tools which work with PyNN.…”

“…The BrainScaleS-2 [52] is a mixed-signal accelerated neuromorphic system with analog neural core, digital connectivity along with embedded SIMD microprocessor. It is efficient for emulations of neurons, synapses, plasticity models etc.…”

PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials

“…In machine learning, algorithmic top-down analysis of the gradient descent demonstrated how local eligibility traces at synapses allow networks to reach performances comparable to error back-propagation algorithm on complex tasks [17]- [19]. Examples of neuromorphic platforms that implement these types of eligibility traces in spiking neural networks already exist [20]- [22]. However, learning in these platforms is only supported through the use of von-Neumann processors, either shared with the computation of network dynamics [21] or a dedicated core [20], [22].…”

“…Examples of neuromorphic platforms that implement these types of eligibility traces in spiking neural networks already exist [20]- [22]. However, learning in these platforms is only supported through the use of von-Neumann processors, either shared with the computation of network dynamics [21] or a dedicated core [20], [22]. Relying on numerical integration, these platforms do not leverage the physics of their computing substrate and are not free from the von-Neumann bottleneck problem [23], [24].…”

On the Role of Information Transfer’s Speed in Technological and Biological Computations

“…In current technological implementations is already 243 noticed that the advantages of using central synchronization are lost, so recently, the idea 244 of asynhronous operation was proposed [30]. In our current technologies, the dispersion is 245 not negligible even within processors, and especially not in computing systems, from the 246 several centimeter long buses in our PCs [11] through the wafer-scale systems [31] to the 247 hundred meter long cables in supercomputers [13].…”