A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS

Tousi, Yahya; Afshari, Ehsan

doi:10.1109/jssc.2011.2162186

Cited by 59 publications

(26 citation statements)

References 31 publications

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“…where C is the capacitance at the charging node, V T is the switching threshold voltage of the inverter, T 0 is the extra delay caused by the invert and I (v in ) is the current controlled by v in [14,17,20]. For short-channel MOSFETs Table 2 The products among the bits of the 3-bit gray code…”

Section: Delay-line Based Adcsmentioning

confidence: 99%

“…In the literature, voltage-based ADCs, which include flash, pipeline and successive approximation (SAR) ADCs, have been widely studied for various applications [1-3, 5, 10, 11, 18, 19, 21]. However, with advances in process technology, voltage-based ADCs cannot be scaled down in terms of power and speed as can digital circuits [17]. Flash ADCs usually use a small feature size to reduce the power consumption with a higher sampling rate.…”

Section: Introductionmentioning

confidence: 99%

“…Time-domain analog-to-digital conversion techniques, which include the voltage-to-time-to-digital approach and the voltage-to-delay-to-digital approach have recently become attractive, especially for deep submicron technologies [8,9,17]. The voltage-to-time-to-digital conversion utilizes a voltage-to-time converter and a time-to-digital converter (TDC) to digitalize input signal, shown in Figure 1(a).…”

Section: Introductionmentioning

confidence: 99%

“…Generally, time-domain ADCs benefit from the advances in fabrication technology. A GHz sampling rate can be easily achieved [9,17]. However, nonlinearity is still an issue, so that the resolution is hardly more than 4 bits with a hundred MHz sampling rate.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Lee

Abraham

2015

J Electron Test

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Delay line ADCs are becoming increasingly attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we first present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. In order to reduce the convergence time of the calibration, we inject a periodic 3-bit gray code sequence instead of three pseudorandom numbers for harmonic distortion correction to digitally calibrate an 8-bit delay line ADC. In our simulation results, the SNDR is significantly improved from 25.6 dB to 42.5 dB, with a calibration time of 13.5 milliseconds, which is 64X faster than harmonic distortion correction with the pseudorandom numbers.

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Section: Delay-line Based Adcsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Lee

Abraham

2015

J Electron Test

View full text Add to dashboard Cite

show abstract

“…Time-domain analog-to-digital conversion techniques, which include the voltage-to-time-to-digital approach and the voltage-to-delay-to-digital approach have recently become attractive, especially for deep submicron technologies [1], [2], [12]. The voltage-to-time-to-digital conversion utilizes a voltage-to-time converter and a time-to-digital converter (TDC) to digitalize input signal, shown in Figure 1(a).…”

mentioning

confidence: 99%

Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction

Lee

Abraham

2013

2013 22nd Asian Test Symposium

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Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delayline ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. This strongly supports the scalability of delay line ADCs and their improved performance in further scaled fabrication processes.

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Floating Gate Transistor‐Based Accurate Digital In‐Memory Computing for Deep Neural Networks

Han

Huang

Xiang

et al. 2022

Advanced Intelligent Systems

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To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in‐memory computing with nonvolatile memory (NVM) is proposed to address the time‐consuming and energy‐hungry data shuttling issue. Herein, a digital in‐memory computing method for convolution computing, which holds the key to DNNs, is proposed. Based on the proposed method, a floating gate transistor‐based in‐memory computing chip for accurate convolution computing with high parallelism is created. The proposed digital in‐memory computing method can achieve the central processing unit (CPU)‐equivalent precision with the same neural network architecture and parameters, different from the analogue or digital–analogue‐mixed in‐memory computing techniques. Based on the fabricated floating gate transistor‐based in‐memory computing chip, a hardware LeNet‐5 neural network is built. The chip achieves 96.25% accuracy on the full Modified National Institute of Standards and Technology database, which is the same as the result computed by the CPU with the same neural network architecture and parameters.

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A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS

Cited by 59 publications

References 31 publications

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction

Floating Gate Transistor‐Based Accurate Digital In‐Memory Computing for Deep Neural Networks

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