A systematic approach to designing high frequency and high power oscillators using activity condition is introduced. This method finds the best topology to achieve frequencies close to the of the transistors. It also determines the maximum frequency of oscillation for a fixed circuit topology, considering the quality factor of the passive components. Using this technique, in a 0.13 m CMOS process, we design and implement 121 GHz and 104 GHz fundamental oscillators with the output power of 3.5 dBm and 2.7 dBm, respectively. Next, we introduce a novel triple-push structure to realize 256 GHz and 482 GHz oscillators. The 256 GHz oscillator was implemented in a 0.13 m CMOS process and the output power of 17 dBm was measured. The 482 GHz oscillator generates 7.9 dBm (0.16 mW) in a 65 nm CMOS process.
Abstract-Nonlinear transmission lines (NLTL) are used for pulse shaping. We developed the theory of pulse propagation through the NLTL. The problem of a wide pulse degenerating into multiple pulses rather than a single pulse is solved by using a gradually scaled NLTL. We exploit certain favorable properties of accumulation-mode MOS varactors to design an NLTL that can simultaneously sharpen both rising and falling edges. There is a good agreement among the theory, simulations, and measurements.
In this paper we will present a low-phase-noise wide-tuning-range oscillator suitable for scaled CMOS processes. It switches between the two resonant modes of a high-order LC resonator that consists of two identical LC tanks coupled by capacitor and transformer. The mode switching method does not add lossy switches to the resonator and thus doubles frequency tuning range without degrading phase noise performance. Moreover, the coupled resonator leads to 3 dB lower phase noise than a single LC tank, which provides a way of achieving low phase noise in scaled CMOS process. Finally, the novel way of using inductive and capacitive coupling jointly decouples frequency separation and tank impedances of the two resonant modes, and makes it possible to achieve balanced performance. The proposed structure is verified by a prototype in a low power 65 nm CMOS process, which covers all cellular bands with a continuous tuning range of 2.5-5.6 GHz and meets all stringent phase noise specifications of cellular standards. It uses a 0.6 V power supply and achieves excellent phase noise figure-of-merit (FoM) of 192.5 dB at 3.7 GHz and 188 dB across the entire tuning range. This demonstrates the possibility of achieving low phase noise and wide tuning range at the same time in scaled CMOS processes.Index Terms-Coupled oscillator, dual band, low phase noise, mode switching, VCO, wide tuning range oscillator.
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